News Article
First 3D Chip Manufacturing Process Developed
Engineers from BeSang, National NanoFab Centre and Stanford University Nano Fab develop first 3D IC manufacturing process.
The National NanoFab Centre (NNFC) in Korea, Stanford NanoFab (SNF) and BeSang, a semiconductor company based in Beaverton, OR, collaborated to successfully develop three dimensional (3D) integrated circuit (IC) technology, enabling low cost memories and high performance logic products with large embedded memory blocks.
This emerging 3D IC technology forms full 3D interconnects below and above the vertical devices, compared to conventional semiconductor technologies with planar devices on the surface of the semiconductor substrate and interconnects only above the planar devices.
3D IC has been processed on 8 inch wafers with industry standard 0.18 um CMOS technologies both at NNFC and SNF. The chip contains 128 million vertically oriented devices as a test vehicle. It is uniquely
processed at low temperatures, below 400 degree Celsius. A sub micron thick single crystalline silicon layer is initially formed above the silicon substrate with two metal interconnect layers, followed by vertical devices and additional metal layer.
"Collaboration with BeSang on 3D IC development demonstrates the expert technical capability of NNFC and the commercialization of emerging semiconductor technologies. We expect that BeSang's breakthrough 3D IC technology will provide ultimate low-cost and high-performance solutions for the semiconductor industry," said Dr. Hee Chul Lee, president of NNFC and professor of Korea Advanced Institute of Science & Technology. "I am pleased that BeSang's 3D IC development is the first success story of excellent collaboration and technology exchange between SNF and NNFC."
"One of unique features of BeSang's 3D IC is the capability of unrestricted 3D interconnections using conventional via technologies that does not require wafer alignment nor through-silicon vias for 3D
interconnects," said Dr. Yoshio Nishi, head of SNF and professor at Stanford University. "Conventional CMOS technology is facing its scaling limits. Therefore, this emerging 3D IC technology will extend the lifespan of CMOS technology, because it is an excellent alternative way to accommodate more devices on a given wafer area."
"BeSang's 3D IC is a novel combination of short process steps, formation of array blocks in 3D, thin layer transfer using unique wafer bonding, followed by low temperature processing," said Dr. Simon Sze,
professor at National Chiao Tung University. "Hence, there is a high possibility for this breakthrough 3D IC to provide low-cost manufacturing solutions for the semiconductor industry. BeSang's 3D IC is a very
attractive technology and one wonders why other companies have not thought about it. However, I always believe in the dynamics of small companies as my colleague, Dawon Kahng, and I worked as a small team within a large organization when we co-invented the non-volatile memory in 1967 at Bell Labs."
"We can imagine evolution of semiconductor technologies through 3D vertical stacking instead of conventional horizontal shrinking which is getting more expensive and facing ever more technical difficulties," said Dr. Dieter Schroder, professor at Arizona State University and on the board of directors of BeSang.
This 3D IC concept has been successfully demonstrated by BeSang at SNF in early 2007 and has been further developed at the commercial level technologies at NNFC since July 2007.
"For rapid wafer processing, engineers at NNFC and students and staff members at SNF reserved the tools for BeSang. With such strong support from NNFC and SNF, BeSang has successfully reached this level of technology development in a very short time. I would like to say special thanks to all at NNFC and SNF," said Sang-Yun Lee, CEO of BeSang.
BeSang's 3D IC technology with vertical devices aims at an innovative, simpler, and more cost effective way to enhance large functional blocks, such as memory arrays or photodiodes for image sensors, systems-on a chip, microprocessors, and memory control logic circuitry in advanced semiconductor chips.
This emerging 3D IC technology forms full 3D interconnects below and above the vertical devices, compared to conventional semiconductor technologies with planar devices on the surface of the semiconductor substrate and interconnects only above the planar devices.
3D IC has been processed on 8 inch wafers with industry standard 0.18 um CMOS technologies both at NNFC and SNF. The chip contains 128 million vertically oriented devices as a test vehicle. It is uniquely
processed at low temperatures, below 400 degree Celsius. A sub micron thick single crystalline silicon layer is initially formed above the silicon substrate with two metal interconnect layers, followed by vertical devices and additional metal layer.
"Collaboration with BeSang on 3D IC development demonstrates the expert technical capability of NNFC and the commercialization of emerging semiconductor technologies. We expect that BeSang's breakthrough 3D IC technology will provide ultimate low-cost and high-performance solutions for the semiconductor industry," said Dr. Hee Chul Lee, president of NNFC and professor of Korea Advanced Institute of Science & Technology. "I am pleased that BeSang's 3D IC development is the first success story of excellent collaboration and technology exchange between SNF and NNFC."
"One of unique features of BeSang's 3D IC is the capability of unrestricted 3D interconnections using conventional via technologies that does not require wafer alignment nor through-silicon vias for 3D
interconnects," said Dr. Yoshio Nishi, head of SNF and professor at Stanford University. "Conventional CMOS technology is facing its scaling limits. Therefore, this emerging 3D IC technology will extend the lifespan of CMOS technology, because it is an excellent alternative way to accommodate more devices on a given wafer area."
"BeSang's 3D IC is a novel combination of short process steps, formation of array blocks in 3D, thin layer transfer using unique wafer bonding, followed by low temperature processing," said Dr. Simon Sze,
professor at National Chiao Tung University. "Hence, there is a high possibility for this breakthrough 3D IC to provide low-cost manufacturing solutions for the semiconductor industry. BeSang's 3D IC is a very
attractive technology and one wonders why other companies have not thought about it. However, I always believe in the dynamics of small companies as my colleague, Dawon Kahng, and I worked as a small team within a large organization when we co-invented the non-volatile memory in 1967 at Bell Labs."
"We can imagine evolution of semiconductor technologies through 3D vertical stacking instead of conventional horizontal shrinking which is getting more expensive and facing ever more technical difficulties," said Dr. Dieter Schroder, professor at Arizona State University and on the board of directors of BeSang.
This 3D IC concept has been successfully demonstrated by BeSang at SNF in early 2007 and has been further developed at the commercial level technologies at NNFC since July 2007.
"For rapid wafer processing, engineers at NNFC and students and staff members at SNF reserved the tools for BeSang. With such strong support from NNFC and SNF, BeSang has successfully reached this level of technology development in a very short time. I would like to say special thanks to all at NNFC and SNF," said Sang-Yun Lee, CEO of BeSang.
BeSang's 3D IC technology with vertical devices aims at an innovative, simpler, and more cost effective way to enhance large functional blocks, such as memory arrays or photodiodes for image sensors, systems-on a chip, microprocessors, and memory control logic circuitry in advanced semiconductor chips.
