Complex Silicon At 0.12microns
"Critical to the development of our 0.12micron CMOS12 process, we put a great deal of effort into ensuring that the design rules were consistent with achieving a high yield when the process came on-stream this year," says Rene Penning de Vries, deputy chief technology officer. "That provided us with very high confidence levels when we migrated our proven 0.18micron cell libraries to 0.12microns, which meant that we were able to put a comprehensive suite of design libraries and tools quickly into the hands of our chip designers." Philips says that rigorous design methodologies have paid off in terms of IP re-use - the guidelines and rules ensuring that hardware IP blocks developed for one process geometry can be quickly migrated to the next process technology node. The design rules for CMOS12 are fully compatible with TSMCs CL013G manufacturing process.