News Article
LSI Logic Claims An Industry First For Copper/low-k
LSI Logic claims an industry first for copper/low-k processes in wire bond
packaging with it Pad on I/O process. This places bond pads directly on top
of active I/O circuits in a chip design. Pad on I/O was developed for LSI
Logic's Gflx (0.11micron) and G90 (90nm) silicon processes. The Pad on I/O
technology can reduce die areas by up to 50% when compared with standard
wire bond designs.
Pad on I/O can be used for in-line or staggered pad designs. For staggered
pad designs, LSI Logic offers the option of designing up to three rows of
staggered pads. Pad on I/O provides a staggered pad pitch of 27microns
effective when compared with the industry standard two-row staggered pad
approach. Pad on I/O is available now and is being used for all wire bond
designs in the company's Gflx and G90 silicon designs.
pad designs, LSI Logic offers the option of designing up to three rows of
staggered pads. Pad on I/O provides a staggered pad pitch of 27microns
effective when compared with the industry standard two-row staggered pad
approach. Pad on I/O is available now and is being used for all wire bond
designs in the company's Gflx and G90 silicon designs.
