News Article
Foundry Process Qualification Guideline Produced.
The Fabless Semiconductor Association (FSA) and JEDEC have produced a
Foundry Process Qualification Guideline. The standard is the work of the FSA
Foundry Process Qualification Subcommittee and the JEDEC JC-14.2 Wafer Level
Reliability Committee.
The document describes a minimum set of requirements to qualify a new
semiconductor wafer process. It is written with particular reference to
generic silicon-based CMOS logic technology. The guideline is also
potentially applicable, with some extensions, to other process technologies
including analogue CMOS, biplolar, BiCMOS and GaAs.
'The Guideline is the culmination of two long years of collaborative effort
by FSA and JEDEC committee members to produce the necessary framework to
help streamline foundry/customer processes,' reports Jodi Shelton,
co-founder and executive director of the FSA.
'We hope this publication will
become the de facto standard for identifying best practices in foundry
process qualification efforts.'
The guideline can be downloaded free of charge from either
www.fsa.org or www.jedec.org
semiconductor wafer process. It is written with particular reference to
generic silicon-based CMOS logic technology. The guideline is also
potentially applicable, with some extensions, to other process technologies
including analogue CMOS, biplolar, BiCMOS and GaAs.
'The Guideline is the culmination of two long years of collaborative effort
by FSA and JEDEC committee members to produce the necessary framework to
help streamline foundry/customer processes,' reports Jodi Shelton,
co-founder and executive director of the FSA.
'We hope this publication will
become the de facto standard for identifying best practices in foundry
process qualification efforts.'
The guideline can be downloaded free of charge from either
www.fsa.org or www.jedec.org
