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Samsung Electronics Has Announced Its 90nm Logic Process Technology, Which

Samsung Electronics has announced its 90nm logic process technology, which will be used to fabricate high capacity memory chips. Samsung is claiming to be the first company to possess the technology for 90nm. There is a long list of other companies with 90nm in various stages of development (Bulletin 446, August 19, 2002).
Samsung has produced samples of 2Gbit NAND Flash on a pilot line and plans















to apply its latest technology to existing fabrication lines by 2003. The















company says that the new technology will lower the cost of producing















current market mainstream 256Mb DRAMs and 512Mb DRAMs by 60%.















The company has already applied this process to produce a working die for a















512Mbit double data rate (DDR) device that complies with the DDR 400















standard and operates at 2.5V. The process uses the long awaited 193nm ArF















lithography, a high-k dielectric composite film technology, and an MNC BL















architecture.































Intel plans to add communications capabilities to its 90nm manufacturing















process (Bulletin 446, August 19, 2002). These capabilities include the use















of high-speed silicon-germanium transistors and mixed-signal circuitry.















Intel's 90nm communications manufacturing process shares the basic















foundation of the company's 90nm logic process, including high-performance,















low-power digital CMOS transistors using strained silicon technology, seven















copper interconnect layers with a new low-k dielectric and 1micron2 SRAM















memory cells. In addition to silicon-germanium heterojunction bipolar















transistors, new features of the 90nm process for communications include















high-voltage RF analogue CMOS transistors, precision capacitors and















resistors for analogue circuits, and high-Q inductors and varactors. Intel















will manufacture all of its 90nm communications chips on 300mm wafers. The















first communications chips based on the new 90nm process are scheduled for















introduction next year.































Intel has also developed a "tri-gate transistor". This uses a 3D structure,















with a raised, flat plateau with vertical sides. Electronic signals travel















both along the top of the transistor and the vertical sidewalls. This















effectively triples the area available for electrical signals to travel















without taking up more space. Besides operating more efficiently at















nanometer-sized geometries, the tri-gate transistor runs faster, delivering















20% more drive current than a planar design of comparable gate size. Intel















is looking to use the tri-gate structure with its fully-depleted silicon on















insulator (SOI) TeraHertz transistor architecture announced in December















2001. The design is also compatible with the future introduction of a high-k















gate dielectric for even lower leakage.















The tri-gate transistor was up for discussion at the International Solid















State Device and Materials conference in Nagoya, Japan, on September 17.







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