News Article
Parthus Technologies Has Licensed Its Phase Lock Loop (PLL) Intellectual
Parthus Technologies has licensed its phase lock loop (PLL) intellectual
property (IP) to the 1st Silicon (Malaysia) foundry. As the first phase of
the agreement, 1st Silicon will verify the Parthus PLL IP in silicon using a
test chip containing multiple PLL instantiations designed to exercise the
extremes of the design range. Further verification will be completed through
simulations using an automated test bench designed to test all valid PLL
configurations in 1st Silicon's 0.25micron and 0.18micron CMOS process
technologies. PLLs are used in clock synthesis cores. Software will be
available to 1st Silicon customers through the Parthus website in October
2002.
Parthus Technologies has licensed its phase lock loop (PLL) intellectual
property (IP) to the 1st Silicon (Malaysia) foundry. As the first phase of
the agreement, 1st Silicon will verify the Parthus PLL IP in silicon using a
test chip containing multiple PLL instantiations designed to exercise the
extremes of the design range. Further verification will be completed through
simulations using an automated test bench designed to test all valid PLL
configurations in 1st Silicon's 0.25micron and 0.18micron CMOS process
technologies. PLLs are used in clock synthesis cores. Software will be
available to 1st Silicon customers through the Parthus website in October
2002.
property (IP) to the 1st Silicon (Malaysia) foundry. As the first phase of
the agreement, 1st Silicon will verify the Parthus PLL IP in silicon using a
test chip containing multiple PLL instantiations designed to exercise the
extremes of the design range. Further verification will be completed through
simulations using an automated test bench designed to test all valid PLL
configurations in 1st Silicon's 0.25micron and 0.18micron CMOS process
technologies. PLLs are used in clock synthesis cores. Software will be
available to 1st Silicon customers through the Parthus website in October
2002.
