News Article
Fast SiGe And Tiny FinFETs
German high performance BiCMOS foundry start-up Communicant Semiconductor
Technologies and its technology partner Innovations for High Performance
microelectronics (IHP) claim best-in-class SiGe:C BiCMOS. A ring oscillator
constructed in the technology has achieved a 4.2ps gate delay. Earlier this
year, IBM reported SiGe ring oscillators with measured time delays of 4.3ps
(Bulletin 421, February 25, 2002).
The heterojunction bipolar transistor (HBT) module offers an fT of 200GHz
and an fmax of 170GHz at a breakdown voltage (BVceo) of 2.0V. IHP's modular
BiCMOS technology eliminates complex processes such as subcollector epi and
deep trenches, giving what Communicant/IHP believe to be the lowest number
of additional lithography levels. The benchmark circuits fabricated include
53-stage CML ring oscillators, static and dynamic dividers, and LC
oscillators.
Details of the benchmarking will be presented at the International Electron
Devices Meeting (IEDM) in San Francisco in December.
AMD says it has fabricated the smallest double-gate transistors reported to
date using standard CMOS technology. The transistors measure 10nm - six
times smaller than the smallest transistors currently in production. Such
miniscule transistors could enable the placement of 1bn transistors on the
same size chip that currently holds 100mn transistors.
Double-gate transistors effectively double the electrical current that can
be sent through a given transistor. The fin field effect transistor (FinFET)
design relies upon a thin vertical silicon "fin" to help control leakage of
current through the transistor when it is in "off" mode.
AMD's laboratory demonstration of 10nm CMOS FinFET is the outcome of
collaborative research with the University of California (UC) Berkeley with
support from the Semiconductor Research Corporation (SRC). The devices were
fabricated in AMD's Submicron Development Center. AMD and UC will present a
paper, "FinFET Scaling to 10nm Gate Length", at the International Electron
Devices Meeting (IEDM), San Francisco, December 9-11, 2002.
TSMC reported on its own FinFET research at the Symposium on VLSI Technology
in Honolulu, Hawaii, in June (Bulletin 437, June 17, 2002). The foundry said
it had succesfully demonstrated devices with 35nm gate lengths and was
moving beyond 25nm in its research. TSMC researchers simulated a 9nm gate
length structure showing it could operate within generally acceptable
parameters.
and an fmax of 170GHz at a breakdown voltage (BVceo) of 2.0V. IHP's modular
BiCMOS technology eliminates complex processes such as subcollector epi and
deep trenches, giving what Communicant/IHP believe to be the lowest number
of additional lithography levels. The benchmark circuits fabricated include
53-stage CML ring oscillators, static and dynamic dividers, and LC
oscillators.
Details of the benchmarking will be presented at the International Electron
Devices Meeting (IEDM) in San Francisco in December.
AMD says it has fabricated the smallest double-gate transistors reported to
date using standard CMOS technology. The transistors measure 10nm - six
times smaller than the smallest transistors currently in production. Such
miniscule transistors could enable the placement of 1bn transistors on the
same size chip that currently holds 100mn transistors.
Double-gate transistors effectively double the electrical current that can
be sent through a given transistor. The fin field effect transistor (FinFET)
design relies upon a thin vertical silicon "fin" to help control leakage of
current through the transistor when it is in "off" mode.
AMD's laboratory demonstration of 10nm CMOS FinFET is the outcome of
collaborative research with the University of California (UC) Berkeley with
support from the Semiconductor Research Corporation (SRC). The devices were
fabricated in AMD's Submicron Development Center. AMD and UC will present a
paper, "FinFET Scaling to 10nm Gate Length", at the International Electron
Devices Meeting (IEDM), San Francisco, December 9-11, 2002.
TSMC reported on its own FinFET research at the Symposium on VLSI Technology
in Honolulu, Hawaii, in June (Bulletin 437, June 17, 2002). The foundry said
it had succesfully demonstrated devices with 35nm gate lengths and was
moving beyond 25nm in its research. TSMC researchers simulated a 9nm gate
length structure showing it could operate within generally acceptable
parameters.
