News Article
Intel Revealed Details Of Its New 90nm Process, Claimed As
Intel revealed details of its new 90nm process, claimed as
"While some are slowly transitioning production to 130nm process on 200mm
wafers, we are moving ahead with the most advanced 90nm technology
exclusively on 300mm wafers," crows Dr Sunlin Chou, senior vice president
and general manager of Intel's Technology and Manufacturing Group.
The transistors have a gate length of 50nm. Intel currently produces
transistors with 60nm gates in its Pentium 4 processor lines. The new
transistors feature gate oxides that are only five atomic layers thick
(1.2nm). The low-k dielectric is a carbon-doped oxide (CDO) material
implemented in a two-layer stack design, which Intel says is easy to
manufacture. A combination of 248nm and 193nm wavelength lithography
equipment is used.
In February, Intel used the 90 nm process to make SRAM chips at 52Mbits with
330mn transistors in an area measuring only 109mm2 (Bulletin 424, March 18,
2002). These devices were manufactured at Intel's 300mm development fab
(D1C) in Oregon, where the process was developed.
"By next year, we will be the first company to have a 90nm process in volume
manufacturing," claims Mark Bohr, Intel Fellow and director of process
architecture and integration.
The company expects to reuse about 75% of the process tools from the current
300mm version of its 0.13micron process. The 90nm process will be ramped
into high volume in D1C and transferred to other 300mm manufacturing fabs
starting next year. Intel expects to have three 300mm wafer fabs using the
90nm process by 2003. One of the first commercial chips to be made on
Intel's process will be the processor codenamed Prescott, which is based on
the NetBurst microarchitecture and will be introduced in H2 2003.
Other companies racing to 90nm are STMicrolectronics, Philips, TSMC,
Motorola, Infineon Technologies, IBM, UMC, Fujitsu, LSI Logic . . .
(Bulletins 419, February 11, 2002; 423, March 11, 2002; 426, April 3, 2002;
428, April 15, 2002; 429, April 22, 2002; 430, April 30, 2002; 436, June 10,
2002; 437, June 17, 2002; 439, July 1, 2002; 444, August 5, 2002; 445,
August 12, 2002).
A European Union Semiconductor Equipment Assessment (SEA) project has been
officially launched to assess Unaxis Semiconductors' LEPECVD 300 low energy
plasma enhanced CVD tool. The work will be carried out at
STMicroelectronics/LETI in Grenoble. This system is designed for high
throughput, low temperature deposition of both silicon and SiGe layers. The
fully automatic bridge tool accepts either 200mm wafers in open cassettes or
300mm in FOUPs. This SEA project will focus on reliability, as well as the
cost of ownership of Unaxis' new production system. The international
project consortium includes ST Microelectronics (France), Motorola (USA),
Picagiga (France) and Wacker (Germany).
The Electronic Device Group of Mitsubishi Electric & Electronics claims the
world's first SOI-CMOS single-chip, 10Gbit Ethernet physical-layer
transceiver LSI (LAN-PHY LSI). The M69850 chip uses a single, 1.8V power
supply. The M69850 is targeted to meet the need to upgrade data transmission
speed in local and metropolitan area networks (LAN & MAN).
Samsung Semiconductor has started mass production of 1Gbit NAND Flash memory
on its 0.12micron process technology. For faster performance, Samsung has
incorporated an expanded page program of 2kBytes and a block erase function
of 128kBytes. A write cache function is included for continuous page
programming, resulting in a 70% increase in speed from previous Samsung NAND
Flash memory devices.
The UK-based ITRI (International Tin Research Institute) reports a number of
complaints from equipment companies that a number of component suppliers are
introducing lead-free versions of existing components, but retaining the
same part numbers. The equipment makers say that this causes considerable
problems, especially if they obtain their components from distributors who
might well mix the two types because they have the same part number. ITRI
acts as a focus and source of information for matters affecting soldering.
wafers, we are moving ahead with the most advanced 90nm technology
exclusively on 300mm wafers," crows Dr Sunlin Chou, senior vice president
and general manager of Intel's Technology and Manufacturing Group.
The transistors have a gate length of 50nm. Intel currently produces
transistors with 60nm gates in its Pentium 4 processor lines. The new
transistors feature gate oxides that are only five atomic layers thick
(1.2nm). The low-k dielectric is a carbon-doped oxide (CDO) material
implemented in a two-layer stack design, which Intel says is easy to
manufacture. A combination of 248nm and 193nm wavelength lithography
equipment is used.
In February, Intel used the 90 nm process to make SRAM chips at 52Mbits with
330mn transistors in an area measuring only 109mm2 (Bulletin 424, March 18,
2002). These devices were manufactured at Intel's 300mm development fab
(D1C) in Oregon, where the process was developed.
"By next year, we will be the first company to have a 90nm process in volume
manufacturing," claims Mark Bohr, Intel Fellow and director of process
architecture and integration.
The company expects to reuse about 75% of the process tools from the current
300mm version of its 0.13micron process. The 90nm process will be ramped
into high volume in D1C and transferred to other 300mm manufacturing fabs
starting next year. Intel expects to have three 300mm wafer fabs using the
90nm process by 2003. One of the first commercial chips to be made on
Intel's process will be the processor codenamed Prescott, which is based on
the NetBurst microarchitecture and will be introduced in H2 2003.
Other companies racing to 90nm are STMicrolectronics, Philips, TSMC,
Motorola, Infineon Technologies, IBM, UMC, Fujitsu, LSI Logic . . .
(Bulletins 419, February 11, 2002; 423, March 11, 2002; 426, April 3, 2002;
428, April 15, 2002; 429, April 22, 2002; 430, April 30, 2002; 436, June 10,
2002; 437, June 17, 2002; 439, July 1, 2002; 444, August 5, 2002; 445,
August 12, 2002).
A European Union Semiconductor Equipment Assessment (SEA) project has been
officially launched to assess Unaxis Semiconductors' LEPECVD 300 low energy
plasma enhanced CVD tool. The work will be carried out at
STMicroelectronics/LETI in Grenoble. This system is designed for high
throughput, low temperature deposition of both silicon and SiGe layers. The
fully automatic bridge tool accepts either 200mm wafers in open cassettes or
300mm in FOUPs. This SEA project will focus on reliability, as well as the
cost of ownership of Unaxis' new production system. The international
project consortium includes ST Microelectronics (France), Motorola (USA),
Picagiga (France) and Wacker (Germany).
The Electronic Device Group of Mitsubishi Electric & Electronics claims the
world's first SOI-CMOS single-chip, 10Gbit Ethernet physical-layer
transceiver LSI (LAN-PHY LSI). The M69850 chip uses a single, 1.8V power
supply. The M69850 is targeted to meet the need to upgrade data transmission
speed in local and metropolitan area networks (LAN & MAN).
Samsung Semiconductor has started mass production of 1Gbit NAND Flash memory
on its 0.12micron process technology. For faster performance, Samsung has
incorporated an expanded page program of 2kBytes and a block erase function
of 128kBytes. A write cache function is included for continuous page
programming, resulting in a 70% increase in speed from previous Samsung NAND
Flash memory devices.
The UK-based ITRI (International Tin Research Institute) reports a number of
complaints from equipment companies that a number of component suppliers are
introducing lead-free versions of existing components, but retaining the
same part numbers. The equipment makers say that this causes considerable
problems, especially if they obtain their components from distributors who
might well mix the two types because they have the same part number. ITRI
acts as a focus and source of information for matters affecting soldering.