News Article
NanoInk Has Released Its First
NanoInk has released its first
DPN builds features by drawing molecules onto a surface with atomic force
microscope (AFM) techniques. Included in the DPN System 1 is DPNWrite, a
software package that uses computer aided design (CAD) to create precise
nano-scale patterns using an AFM. The software employs a layering process,
similar to programs for integrated circuit design, to design and draw DPN
patterns for use with different molecular inks.
The technique was developed by NanoInk cofounder, Professor Chad Mirkin,
director of the Northwestern University Nanotechnology Institute (Bulletins
307, October 22, 1999; 339, June 13, 2000; 437, April 8, 2002).
Researchers from the RWTH Aachen, Stepanov Institute of Physics, Minsk and
.AIXTRON presented the first optically pumped blue laser chip based on
InGaN/GaN using a silicon wafer substrate during the IWN (International
Workshop on Nitrides) conference in Aachen, Germany. The blue laser
wavelength was 447nm with a maximum operation temperature of 420K, a low
threshold to achieve the lasing of 270kW/cm2 and an output power of 8W.
These performance characteristics are close to that of lasers grown on much
more expensive sapphire and SiC substrates. Silicon wafers can be up to ten
times cheaper than SiC or sapphire and are also available in much larger
diameters - up to 300mm. Like SiC wafers, they offer high levels of thermal
conductivity. By contrast insulating sapphire wafers are thermally
insulating, which can create heating problems.
Applied Materials released details of its integrated atomic layer
deposition/physical vapour seposition (ALD/PVD) product, the Endura iCuB/S
integrated copper barrier/seed system. The technology is designed to deposit
critical barrier and seed layers in 65nm-generation and beyond copper
interconnects. The "breakthrough" iCuB/S system deposits an ultrathin,
conformal tantalum nitride (TaN) barrier layer that is compatible with
advanced low-k dielectric films, says Applied. The company has demonstrated
integration with its Black Diamond low k film at the Applied's Process
Module Technology Center. Applied Materials claims short cycle times and
very low defect densities for its ALD TaN chamber with a throughput
comparable to PVD. The chambers are mounted on the company's Endura XP
mainframe.
SI Diamond Technology subsidiary Applied Nanotech has introduced two
proprietary products based on nanotechnology -- carbon nanotube gated
electron sources (triode structures) and colloidal solutions of silicon
nanocrystals (quantum dots).
Applied Nanotech believes the carbon nanotube gated electron sources are the
first commercially available electron sources based on carbon nanotubes. The
integrated gate modulates the electron emission characteristics with
voltages of approximately 400V. ANI currently supplies on a commercial basis
diode mode (without gate) electron sources based on carbon nanotechnology
for applications such as x-ray spectrometers for industrial applications and
miniature x-ray tubes for medical applications. The new triode mode
structures are designed to lower the control voltages to less than 100V,
thereby reducing the cost and extending the lifetime of the devices.
The silicon nanocrystals (quantum dots) are seen as enabling silicon to be
used in visible light optoelectronics. ANI is able to deliver today
quantities of silicon nanocrystals in colloidal solutions at a price of
$100/mg.
The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) will
install a complete 300mm line for wafer bumping and wafer-level packaging
(WLP) in Asia using electroplate technology. The line will be installed at
the facility of Unitive's affiliated company UST in Hsinchu, Taiwan. The
facility will demonstrate and provide high-volume manufacturing capability.
The line will be installed in Q4 2002 and operations will begin in Q1 2003.
"The industry's transition to 300mm technology thus far has focused heavily
on front-end equipment and process issues," says Franz Richter, SUSS
MicroTec CEO. "But back-end processes also need to be performed at the
wafer-level. Interest in 300mm process equipment for wafer bumping and
wafer-level packaging has increased significantly in the last 12 months, not
only for microprocessors including FPGAs, ASICs, graphical chip sets and
memory devices."
The facility will be a joint venture between Unitive and the equipment
suppliers within SECAP. These tool suppliers will participate in the line
with installation of their latest 300mm equipment, including SECAP's newest
member NEXX Systems (Bulletin 440, July 8, 2002). Unitive will invest in
equipment, ancillary support equipment and infrastructure to support the
line.
According to the SECAP charter, SECAP will remain neutral to all packaging
technologies - as such, Unitive will not become a member of SECAP. The SECAP
consortium does not intend to develop or market packaging technologies,
since its purpose is to create a non-competitive environment for its
customers. The members of SECAP are Semitool, Suss MicroTec, Image
Technology, Matrix Integrated Systems, NEXX Systems, Electroglas and the
Fraunhofer Institute for Reliability and Microintegration (IZM) in Berlin,
Germany.
International SEMATECH's (ISMT) Interconnect Division has transferred its
low-k baseline process for 200mm to pilot manufacture in ISMT's cleanroom
(Advanced Technology Development Facility or ATDF) a month ahead of
schedule. The low-k baseline dual Damascene process flow uses JSR's LKD-5109
porous spin-on dielectric material.
"The insertion of low-k materials into manufacturing is taking longer than
expected due to a number of issues, including low strength, poor adhesion,
and DUV photo resist poisoning," reports Rod Augur, ISMT's program manager
for Cu/low-k interconnect integration. "Nevertheless, the International
Technology Roadmap for Semiconductors still calls for low-k values that are
only available with porous materials, which places further constraints on
unit processes."
Augur believes a steady supply of samples for development by process,
chemical, and tool suppliers is needed to help solve the integration issues
of porous ultra low-k materials. ISMT's new low-k baseline will provide such
samples.
LKD-5109 is a MSQ (methylsilsesquioxane) based dielectric with a k of 2.2
and pore diameter of 2nm. ISMT's baseline process flow uses a dual top hard
mask approach (to make litho rework easier), standard Cu electroplating, and
conventional CMP (chemical mechanical planarisation). The flow was
transferred to ISMT's ATDF on May 31, 2002. Current yields regularly exceed
85% on 0.25micron 360k via chains. Continual process improvement is planned
to increase both yield and performance. By year-end, International SEMATECH
will qualify the low-k flow on 300mm wafers. ISMT is planning a move to
130nm actual feature sizes in early 2003.
Test wafers developed with LKD-5109 are now available through ISMT for etch,
cleans, deposition and CMP studies. The wafers will be offered to
semiconductor companies on a limited basis under a supplier agreement
between ISMT and JSR.
NASA's Jet Propulsion Laboratory has developed a four-band quantum well
infrared photodetector (QWIP) camera with sensitivity at wavelengths up to
15.5microns. Each band or focal plane measures 128x640 pixels. JPL believes
a 64-band detector could be possible. Applications include pollution
detection and weather prediction.
Ashland Specialty Chemical and Semitool are to jointly develop wet chemical
cleaning techniques for the semiconductor industry. The particular focus
will be processes for integrated low-k/copper metallisation.
Semiconductor assembly and test company Advanced Interconnect Technologies
introduced a family of system-in-package (SIP) plastic land grid arrays
(PLGAs) for use in cellular phones, personal digital assistants (PDAs),
digital cameras and MP3 players.
Advanced Semiconductor Engineering (ASE) has developed a tri-tier fine pitch
(FP) wire bonding process where three rows of wiring protrude from the IC
pads to provide connectivity to other parts of the IC package. The inner,
middle and outer wires are isolated by different loop heights to prevent
wire shorting.
ASE's tri-tier wire bonding technology is suitably applied to ICs that
require the integration of multiple functions onto a limited area such as
the chipsets within PCMCIA and multimedia/graphics cards in desktop and
notebook PCs. The company currently offers its tri-tier FP wire bonding
process in plastic ball grid arrays (PBGA) as low as 70microns and will
offer down to 60microns at the end of 2002. US and Taiwan patents were
granted in 2001.
microscope (AFM) techniques. Included in the DPN System 1 is DPNWrite, a
software package that uses computer aided design (CAD) to create precise
nano-scale patterns using an AFM. The software employs a layering process,
similar to programs for integrated circuit design, to design and draw DPN
patterns for use with different molecular inks.
The technique was developed by NanoInk cofounder, Professor Chad Mirkin,
director of the Northwestern University Nanotechnology Institute (Bulletins
307, October 22, 1999; 339, June 13, 2000; 437, April 8, 2002).
Researchers from the RWTH Aachen, Stepanov Institute of Physics, Minsk and
.AIXTRON presented the first optically pumped blue laser chip based on
InGaN/GaN using a silicon wafer substrate during the IWN (International
Workshop on Nitrides) conference in Aachen, Germany. The blue laser
wavelength was 447nm with a maximum operation temperature of 420K, a low
threshold to achieve the lasing of 270kW/cm2 and an output power of 8W.
These performance characteristics are close to that of lasers grown on much
more expensive sapphire and SiC substrates. Silicon wafers can be up to ten
times cheaper than SiC or sapphire and are also available in much larger
diameters - up to 300mm. Like SiC wafers, they offer high levels of thermal
conductivity. By contrast insulating sapphire wafers are thermally
insulating, which can create heating problems.
Applied Materials released details of its integrated atomic layer
deposition/physical vapour seposition (ALD/PVD) product, the Endura iCuB/S
integrated copper barrier/seed system. The technology is designed to deposit
critical barrier and seed layers in 65nm-generation and beyond copper
interconnects. The "breakthrough" iCuB/S system deposits an ultrathin,
conformal tantalum nitride (TaN) barrier layer that is compatible with
advanced low-k dielectric films, says Applied. The company has demonstrated
integration with its Black Diamond low k film at the Applied's Process
Module Technology Center. Applied Materials claims short cycle times and
very low defect densities for its ALD TaN chamber with a throughput
comparable to PVD. The chambers are mounted on the company's Endura XP
mainframe.
SI Diamond Technology subsidiary Applied Nanotech has introduced two
proprietary products based on nanotechnology -- carbon nanotube gated
electron sources (triode structures) and colloidal solutions of silicon
nanocrystals (quantum dots).
Applied Nanotech believes the carbon nanotube gated electron sources are the
first commercially available electron sources based on carbon nanotubes. The
integrated gate modulates the electron emission characteristics with
voltages of approximately 400V. ANI currently supplies on a commercial basis
diode mode (without gate) electron sources based on carbon nanotechnology
for applications such as x-ray spectrometers for industrial applications and
miniature x-ray tubes for medical applications. The new triode mode
structures are designed to lower the control voltages to less than 100V,
thereby reducing the cost and extending the lifetime of the devices.
The silicon nanocrystals (quantum dots) are seen as enabling silicon to be
used in visible light optoelectronics. ANI is able to deliver today
quantities of silicon nanocrystals in colloidal solutions at a price of
$100/mg.
The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) will
install a complete 300mm line for wafer bumping and wafer-level packaging
(WLP) in Asia using electroplate technology. The line will be installed at
the facility of Unitive's affiliated company UST in Hsinchu, Taiwan. The
facility will demonstrate and provide high-volume manufacturing capability.
The line will be installed in Q4 2002 and operations will begin in Q1 2003.
"The industry's transition to 300mm technology thus far has focused heavily
on front-end equipment and process issues," says Franz Richter, SUSS
MicroTec CEO. "But back-end processes also need to be performed at the
wafer-level. Interest in 300mm process equipment for wafer bumping and
wafer-level packaging has increased significantly in the last 12 months, not
only for microprocessors including FPGAs, ASICs, graphical chip sets and
memory devices."
The facility will be a joint venture between Unitive and the equipment
suppliers within SECAP. These tool suppliers will participate in the line
with installation of their latest 300mm equipment, including SECAP's newest
member NEXX Systems (Bulletin 440, July 8, 2002). Unitive will invest in
equipment, ancillary support equipment and infrastructure to support the
line.
According to the SECAP charter, SECAP will remain neutral to all packaging
technologies - as such, Unitive will not become a member of SECAP. The SECAP
consortium does not intend to develop or market packaging technologies,
since its purpose is to create a non-competitive environment for its
customers. The members of SECAP are Semitool, Suss MicroTec, Image
Technology, Matrix Integrated Systems, NEXX Systems, Electroglas and the
Fraunhofer Institute for Reliability and Microintegration (IZM) in Berlin,
Germany.
International SEMATECH's (ISMT) Interconnect Division has transferred its
low-k baseline process for 200mm to pilot manufacture in ISMT's cleanroom
(Advanced Technology Development Facility or ATDF) a month ahead of
schedule. The low-k baseline dual Damascene process flow uses JSR's LKD-5109
porous spin-on dielectric material.
"The insertion of low-k materials into manufacturing is taking longer than
expected due to a number of issues, including low strength, poor adhesion,
and DUV photo resist poisoning," reports Rod Augur, ISMT's program manager
for Cu/low-k interconnect integration. "Nevertheless, the International
Technology Roadmap for Semiconductors still calls for low-k values that are
only available with porous materials, which places further constraints on
unit processes."
Augur believes a steady supply of samples for development by process,
chemical, and tool suppliers is needed to help solve the integration issues
of porous ultra low-k materials. ISMT's new low-k baseline will provide such
samples.
LKD-5109 is a MSQ (methylsilsesquioxane) based dielectric with a k of 2.2
and pore diameter of 2nm. ISMT's baseline process flow uses a dual top hard
mask approach (to make litho rework easier), standard Cu electroplating, and
conventional CMP (chemical mechanical planarisation). The flow was
transferred to ISMT's ATDF on May 31, 2002. Current yields regularly exceed
85% on 0.25micron 360k via chains. Continual process improvement is planned
to increase both yield and performance. By year-end, International SEMATECH
will qualify the low-k flow on 300mm wafers. ISMT is planning a move to
130nm actual feature sizes in early 2003.
Test wafers developed with LKD-5109 are now available through ISMT for etch,
cleans, deposition and CMP studies. The wafers will be offered to
semiconductor companies on a limited basis under a supplier agreement
between ISMT and JSR.
NASA's Jet Propulsion Laboratory has developed a four-band quantum well
infrared photodetector (QWIP) camera with sensitivity at wavelengths up to
15.5microns. Each band or focal plane measures 128x640 pixels. JPL believes
a 64-band detector could be possible. Applications include pollution
detection and weather prediction.
Ashland Specialty Chemical and Semitool are to jointly develop wet chemical
cleaning techniques for the semiconductor industry. The particular focus
will be processes for integrated low-k/copper metallisation.
Semiconductor assembly and test company Advanced Interconnect Technologies
introduced a family of system-in-package (SIP) plastic land grid arrays
(PLGAs) for use in cellular phones, personal digital assistants (PDAs),
digital cameras and MP3 players.
Advanced Semiconductor Engineering (ASE) has developed a tri-tier fine pitch
(FP) wire bonding process where three rows of wiring protrude from the IC
pads to provide connectivity to other parts of the IC package. The inner,
middle and outer wires are isolated by different loop heights to prevent
wire shorting.
ASE's tri-tier wire bonding technology is suitably applied to ICs that
require the integration of multiple functions onto a limited area such as
the chipsets within PCMCIA and multimedia/graphics cards in desktop and
notebook PCs. The company currently offers its tri-tier FP wire bonding
process in plastic ball grid arrays (PBGA) as low as 70microns and will
offer down to 60microns at the end of 2002. US and Taiwan patents were
granted in 2001.
