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The US National Electronics Manufacturing Initiative (NEMI) Has Launched A

The US National Electronics Manufacturing Initiative (NEMI) has launched a
The new project is to develop robust lead-free assembly and rework processes
for printed circuit board (PCB) assemblies using the NEMI-recommended
lead-free solder -- Sn3.9Ag0.6Cu. The project will be working with hybrid
assemblies, representing high-end office computer products that use both
surface mount technology (SMT) and pin-in-hole (PIH) components.
"Transition to lead-free assemblies presents several issues and challenges
for electronics manufacturers because lead-free solders require processing
temperatures that are approximately 30-40C above the temperatures used
today," says Jerry Gleason, co-chair of the new NEMI project and a member of
the technical staff in Hewlett-Packard Company's Electronic Systems
Technology Center.
Project work will be executed by four teams: Test Vehicle & Qualification
Build, Assembly, Rework and Reliability Testing. The projected completion
date is February 2004. Companies participating in development of the project
include AMD, Agilent Technologies, Alcatel Canada, BTU International,
Celestica, ChipPAC, Cookson Electronics, Hewlett-Packard, IBM, Intel
Corporation, Jabil Circuits, Nortel Networks, Plexus, Sanmina-SCI,
Solectron, SUNY-Binghamton, Teradyne, Texas Instruments and Vitronics
Soltec.

Fujitsu Microelectronics introduced its CS Module - a wafer-level chip-size
module with system-in-package technology. The technology combines
wafer-thinning with chip stacking and redistribution. The wafer grinding on
the rear face of the wafer reduces the thickness the standard 0.15mm to
0.025mm, reducing the wafer to approximately 16 percent of its original
thickness.
The CS Module includes four chips designed for high-end applications. The
modules use two logic devices placed on top of each other, along with a
memory chip. The upper-stage chip spacing is at a pitch of 0.040mm. Using
0.050mm thick devices, the module achieves a maximum density of 0.65mm.

FSI International has developed a process for selective etch of high-k
silicates. The company claims that the new process chemistry implemented on
its immersion and spray tools has demonstrated an unprecedented etch rate
(up to 80Angstroms/minute) and a selectivity to tetraethyl orthosilicate
(TEOS) deposited oxide as high as 16:1 on hafnium silicates. The company is
looking to meet the needs of high-k silicate gates for the 65nm technology
node used to replace silicon dioxide.
The process chemistry has been demonstrated on several silicates, including
hafnium silicate and zirconium silicate. The hafnium silicate - with a k
value of 12-14 - can be implemented on existing chemical vapour deposition
(CVD) tools. The effective gate oxide thickness for this material can
approach 1nm.
FSI worked on the process at International SEMATECH (ISMT), the global
consortium of semiconductor manufacturers. The International Technology
Roadmap for Semiconductors (ITRS) timetables 65nm technology node pliots for
2004 with production use by 2007.

Infineon Technologies is to lead a EUR4.5m European Union development
project on atomic layer depostion. The full title of the project is "High
Throughput Atomic Layer Chemical Vapour Deposition Batch Equipment using
Remote Plasma Enhanced Processing and In-Situ Chamber Clean" (HALE&RAPID).
The duration of the programme is 18 months. Funding of EUR1.86m is to come
from the European Commission's Fifth Framework Programme (5th FWP). Other
participants are Motorola, Austriamicrosystems, ASM International and the
Fraunhofer Institute.

US non-leading edge lithography system producer Ultratech Stepper is looking
for business in the "nanotechnology" market. Specifically, the
"nanotechnology" market seems to be defined by the company as
micro-electro-mechanical systems (MEMS), which perhaps should rather be
described as "microtechnology". Normally, the term "nanotechnology" is
restricted to sub-100nm resolutions and structures. The company has launched
a family of five "NanoTech" steppers, each based on an existing Ultratech
system. These products seem to be aimed at resolutions in the 0.75-2.0micron
range. Beta testing is due to begin in Q4 2002 with production versions out
in January 2003.

Tokyo Electron (TEL) reports improved performance using a low-k material
with dielectric constant of 2.2 in an integrated dual level metal
copper/low-k module. The integration results were produced on TEL's
integrated low-k toolset, which includes the CLEAN TRACK ACT
coater/developer, the UNITY etch system, the ALPHA-8SE thermal processing
tool, and the PR200Z cleaning system. The wafer processing was handled
through International SEMATECH's wafer services programme. The purpose of
the work was to evaluate three wet cleaning chemistries for the low-k
dielectric. The PR200Z proved to enhance cleaning efficiency due to the
system's hybrid process capability that resulted in lower defects and higher
yields. The results of the BEOL research proved better than ISMT's standard
qualified process for low-k dielectrics.
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