Process Development
advanced smartcard memory technology. Page Flash aims to remove the need for
EEPROM (electrically erasable programmable read-only memory) in high memory
density smartcard chips.
A smartcard technology demonstrator combines a 32-bit secure microcontroller
with 1MByte of Flash memory. This demonstrator was developed within the
European Union MEDEA+ project [email protected] and codenamed ST22FJ1M.
EEPROM offers program/erase speeds of a few milliseconds but requires a
relatively high voltage (18V) to be applied during the write process. New
smaller process generations make it increasingly difficult to design devices
that can withstand 18V, limiting EEPROM scalability.
Page Flash is a derivative of standard Flash technology. Standard Flash
offers large sector erasure in around 1s and fast programming of about
10microsecs. Page Flash offers the same fast programming time as Standard
Flash but also allows individual data words (32-bits) to be erased in a few
milliseconds and to rewritten more than 100,000 times.
The two types of Flash can be mixed on the same chip at no additional cost
and without any modification to the standard Flash manufacturing process.
At the beginning of 2003, the concepts developed and validated on the
ST22FJ1M demonstrator will be used to create a range of products based upon
the ST22 core with Flash/Page Flash.
Epson Europe Electronics and Swedish Advanced Technology Systems (Swats) are
developing a smartcard with integrated display. The Swats DisplayCard will
use an electrophoretic dotmatrix display.
"Our development team is currently working on the production machine which
will manufacture the display cards," reports Olov Holst, executive
vice-president of Swats. "The production process is patented. We are in
negotiation with some of the largest card manufacturers in the world
regarding a license agreement, and plan mass production of the Swat
DisplayCard to start in 2004."
The first project will be a bank card that allows customers to see their
balance and transaction record.
Philips Electronics is aiming at the market for the industrys highest-speed
DVD+R/RW (DVD+Recordable/ReWriteable) recorders with a package including a
chipset, optical pickup unit (OPU), firmware and reference design. The DVD
design incorporates new technology to minimise recording errors caused by
common disk defects such as fingerprints. The software and chipset is based
on Philips Nexperia streaming media technology. The reference spec would
allow creation of 4.7GByte DVDs in less than 15 minutes - or half the time
of existing drives, says Philips.
The chipset includes a PNX7850 main processor, a TZA1039 analogue processor
and a TZA1047 laser power controller. The entire system is designed to work
with Philips OPU66.20. A sample kit including the chipset and OPU is
available now. The kit will cost $65 each in volumes of 100,000 units.
Volume production is scheduled for Q1, 2003.
Infineon Technologies is pushing "multi-threaded execution" as a means to
increase the performance of embedded computing without going to higher
performance chips. Embedded processors are used in mobile phone, PDAs,
peripherals, automobiles and other consumer applications. Multi-threading,
says Infineon, will enable embedded system designers to "jump over the
limitations of Moores Law and achieve up to a 10x increase in the
efficiency of new processors".
Multi-threading was developed for high performance computer systems and is
being applied by Intel to its latest high performance microprocessor chips.
Infineon says it has developed a series of innovations that make it possible
to use multi-threading in the lower performance domain of embedded systems
(microcontrollers, microprocessors, digital signal processors). This is
achieved while maintaining or even improving the real-time determinism
needed for embedded systems. Infineons first application will be in a
32-bit microcontroller planned for introduction in the middle of next year.
The company also plans licensing the technology to others.
Multi-threading creates a series of multiple "virtual processors" on one
physical device - when one task (such as a memory access) is forced to wait,
another takes over. Infineon sees multi-threading as being particularly
useful in reducing memory cost, allowing slower devices to be used more
often. Other improvements available from multi-threading include systems
running at lower speed and lower power consumption.
Texas Instruments has produced a 64Mbit ferroelectric RAM (FRAM) chip within
a standard CMOS logic process. TI says FRAM has advantages over other
embedded memory options in terms of manufacturing costs and power
consumption.
TI also claims that the device has the smallest FRAM cells ever reported, a
mere 0.54microns2. The test chips were produced using the companys standard
130nm, copper-interconnect process with only two additional mask steps. At
the 90nm process node - the generation where TIs first embedded FRAM
products are expected to appear - the FRAM cells will be even smaller, a
mere 0.35microns2. The capacitor is formed using iridium electrodes and a
thin lead zirconate titanate (PZT) ferroelectric layer.
In August of 2001, TI made a multi-million dollar FRAM memory licensing and
development agreement with US ferroelectric memory developer Ramtron
International. Additional technical details on TIs FRAM technology will be
presented during the International Electron Devices Meeting (IEDM), December
8-11, 2002, San Francisco, California.
US company SiidTech has signed a joint technology development agreement with
Japans Hitachi ULSI Systems to combine their respective semiconductor
identification technologies. Both companies have independent technology
based on the random parametric variations that occur during semiconductor
manufacturing.
Each company will develop semiconductor intellectual property (SIP) products
for applications ranging from semiconductor manufacturing yield enhancement
and die tracking, to smart ID, security and authentication, and encryption.
SiidTechs "Silicon Fingerprinting" process is delivered in the form of a
hard IP cell that occupies a space of about 100x100microns in a standard
0.18micron CMOS process. The unique identification number (or Silicon
Fingerprint) is produced without any extra programming steps.
Hitachi ULSI becomes the exclusive marketer and distributor for both
companies products and services to semiconductor and systems houses in
Asia. Hitachi ULSI will also have a licensing agreement for all SiidTechs
SIP. The first products from the joint work are to be available by mid 2003.
Semiconductor identification technology allows tracking of chips after their
incorporation into larger assemblies or system products. Such a tracking
capability can be used to identify defective ICs or assemblies/systems by
providing a means to identify the particular part and its manufacturing
history and/or channel of distribution. At semiconductor-manufacturing
sites, the technology can be used to contribute to yield improvement by
providing means to investigate and analyse failure modes for particular ICs.
