Onward To 65nm
. The new processes are the result of joint development at Toshiba and Sony initiated in May 2001. Full details will be presented at the International Electron Devices Meeting (IEDM), December 9-11.
The basic component of the 65nm technology is a high-performance transistor with a 30nm gate length. Gate leakage currents are suppressed through a high nitrogen concentration plasma nitrided oxide dielectric. Leakage is reduced some 50 times more efficiently than a conventional SiO2 film.
The effective oxide thickness is only 1nm. Ni silicide is applied in the gate electrodes and source/drain regions to attain low resistance and to reduce junction leakage currents.
. Ultra-low energy ion implantation - with a spike rapid thermal anneal (RTA) and offset spacer process - is used to create shallow source/drain extensions. These suppress the MOSFET short channel effect. The NMOSFET switching speed is 0.72psec. The slower PMOSFET switches at 1.41psec. These figures were obtained at 0.85V (Ioff=100nA/um).
The process also implements high numerical aperture (NA) 193nm lithography with an alternating phase shift mask and slimming process. The first metal layer on the 65nm process has a pitch of 180nm - a 75% shrink from the 90nm generation. To reduce wiring propagation delay and power dissipation, a low-k dielectric material is adopted. The target effective dielectric constant of the interlayer dielectric is around 2.7.
Toshiba says it is the only company with mass production technology for 90nm process embedded DRAM. The 90nm technology is currently in the deployment phase. Toshiba and Sony have produced embedded DRAM cells of 0.11micron2 area on the 65nm process. This allows a memory capacity of more than 256Mbit to be integrated on a single chip. The companies believe they can achieve the worlds smallest embedded SRAM cell in the 65nm generation with areas of only 0.6micron2.
