Pushing Technology

ST will be presenting six papers - four concern CMOS technology and the remaining two non-volatile memory.
One paper by researchers from ST Agrate reports detailed investigation of the electronic switching effects in chalcogenide-based phase-change devices (ovonic unified memory - OUM).

This technology is related to that of rewritable CDs. ST believes the technology is the best candidate to complement and eventually replace Flash memory based on superior performance and better scalability. A numerical model based on band-gap considerations for both crystalline and amorphous chalcogenide is proposed to account for both the DC and transient I-V device characteristics.

A joint team from ST, France Telecom R&D, CEA-LETI and Philips Semiconductors will describe 40nm n-channel MOSFETs featuring polysilicon gates and an HfO 2 gate dielectric. The performances obtained were similar to those of transistors built using conventional SiO 2 dielectric but exhibited leakage currents around 100 times smaller - believed to be the highest performance ever reported for pure HfO 2 with a polysilicon gate. ST and another group of research par tners will also describe and characterise the world's first NMOS and PMOS transistor integration using a damascene CVD TiN/W metal gate and a hafnium dioxide high-k dielectric.

ST and its research partners France Telecom R&D and CEA-LETI will also describe the world's first “silicon-on-nothing” (SON)transistor with totally silicided gates. The architecture allows extremely thin buried dielectrics and silicon films, no more than a few nanometers thick, to be fabricated with high accuracy within the methodologies of conventional epitaxy.

Measurements on a PMOS transistor with a 55nm silicided metal gate and a very thin(5nm) silicon conduction channel showed an off-state current reduced by orders of magnitude compared with polysilicon gates.

IBM has produced silicon transistors that are 6nm long, claimed as the world's smallest. The leading edge is around 130nm with 90nm and 65nm in development. The industry's 2001 International Technology Roadmap for Semiconductors (ITRS) organisation seeks to develop transistors smaller than 9nm by 2016. IBM says it is the first company to make working transistors below that gate length. Because smaller transistors are more difficult to turn on and off, IBM has used a reduced silicon thickness on bonded silicon-on-insulator (SOI) wafers. The silicon body of the 6nm gate transistor is only 4-8nm thick to achieve appropriate turn-on and turn-off behaviour. IBM believes that aggressive thinning of the SOI layer is a promising option to drive CMOS device scaling. Halo implants and 248nm-wavelength lithography were used to create the transistor structures. IBM is presenting details in a paper entitled “Extreme
Scaling with Ultra-thin Silicon Channel MOSFETs”.

Toshiba and Sony are claiming the world's first 65nm CMOS process technology for embedded DRAM system LSI (large scale integration) chips. The new processes are the result of joint development at Toshiba and Sony initiated in May 2001.

The basic component of the 65nm technology is a high-performance transistor with a 30nm gate length. Gate leakage currents are suppressed through a high nitrogen concentration plasma nitrided oxide dielectric. Leakage is reduced some 50 times more efficiently than a conventional SiO 2 film. The effective oxide thickness is only 1nm. Ni silicide is applied to the gate electrodes and source/drain regions to attain low resistance and to reduce junction leakage currents.

Ultra-low energy ion implantation - with a spike rapid thermal anneal (RTA) and offset spacer process - is used to create shallow source/drain extensions. These suppress the MOSFET short channel effect. The NMOSFET switching speed is 0.72psec. The slower PMOSFET switches at 1.41psec. These figures were obtained at 0.85V (I off =100nA/µm).

The process also implements high numerical aperture (NA)193nm lithography with an alternating phase shift mask and slimming process. The first metal layer on the 65nm process has a pitch of 180nm - a 75% shrink from the 90nm generation. To reduce wiring propagation delay and power dissipation, a low-k dielectric material is adopted. The target effective dielectric constant of the interlayer dielectric is around 2.7.

Toshiba says it is the only company with mass production technology for 90nm process embedded DRAM. The 90nm
technology is currently in the deployment phase.

Toshiba and Sony have produced embedded DRAM cells of 0.11µm 2 area on the 65nm process. This allows a memory capacity of more than 256Mbit to be integrated on a single chip. The companies believe they can achieve the world's smallest embedded SRAM cell in the 65nm generation with areas of only 0.6µm 2 .