Process Development
power and performance specifications outlined by the International
Technology Roadmap for Semiconductors (ITRS).
The operating voltage is just 0.7V producing a gate delay of 0.39psecs for
n-type transistors and 088psecs for p-type. The device is a newly designed
FinFET produced on a 25nm CMOS process. TSMC has also produced functional
SRAM cells using the new transistors.
FinFETs have the shape of tiny fish fins. A number of companies are
developing devices based on this concept. TSMCs new FinFET version is known
as the "Omega FinFET", because the gate "wraps" around the silicon material
that makes up the source and drain for each gate. This creates a structure
similar to the Greek character, omega. TSMC says that the FinFETs were
fabricated with TSMCs standard production equipment and materials.
"To meet aggressive new transistor performance targets, many research
efforts have turned to higher voltages and larger leakage than the Roadmap
targets," comments Dr Chenming Hu, TSMCs chief technology officer.
"Unfortunately, these compromises shorten the battery life and create heat
removal problems. Our FinFET design successfully achieves targets for high
speed, low voltage and low leakage, thereby satisfying the low power
requirements of the ITRS roadmap and the application space of tomorrow."
A new Xilinx field programmable gate array (FPGA) chip design has been taped
out for production in IBMs new 300mm chip fab. The companies believe that
this is a major step towards the worlds first 90nm production chip. The new
process technology has resulted in a 50-80% FPGA chip-size reduction
compared with any competing FPGA solution, it is claimed. IBM plans to
manufacture the new product line in volume in H2 2003 at East Fishkill, New
York state. The new facility began operation this year, and will be ramping
up in capacity throughout 2003.
Infineon Technology reports that its per chip production on 300mm wafers now
costs less than its 200mm technology. The company has been producing in
"volume" for just over a year at its Dresden facility in Germany. The plant
is due to reach full capacity - 28,000 wafer starts per month - by next
summer. Current capacity is 19,000 300mm wafer starts. Chief operating
officer Dr Andreas von Zitzewitz believes the company has a "four to five
year lead over the competition" in converting to 300mm DRAM production. The
current feature size is 0.14microns with 0.11microns planned for next year.
Innovative Micro Technology (IMT) has been awarded $1.8mn from the Defense
Advanced Research Projects Agency (DARPA) and the US Army to develop a next
generation biological cell purification technology based on recent advances
in micro-electro-mechanical systems (MEMS). The purpose of this award is to
develop a high-speed system for purification of human blood stem cells, as
part of DARPAs goal to develop an ex-vivo immune system. The project is
part of DARPAs Engineered Tissue Constructs programme.
Dr John Foster, IMTs CEO, explains: "The device to be developed under this
grant incorporates massively-parallel MEMS devices to rapidly and easily
purify cells for therapeutic and research applications."
The potential outcome of this DARPA project is the development of an
effective tissue engineering approach to generate an immune system outside
of the body as a test bed for developing protection against bioterrorism.
IC assembly and packaging company Advanced Semiconductor Engineering (ASE)
says it is ready for volume production of two image sensor package types - a
ceramic leadless chip carrier (CLCC) and an organic leadless chip carrier
(OLCC).
The CLCC consists of three layers of ceramic substrate with a glass lid.
This product is aimed at the high-end image sensor market with large IC
package size at 1.3Mpixels or better. The OLCC has an organic BT substrate
for lower cost.
DuPont Displays and Universal Display (UDC) have agreed joint development of
a new generation of soluble organic light emitting diode (OLED) materials
and technology. The agreement aims at combining the best elements of
research into both small molecule OLED and solution process OLED materials.
The collaborators expect to use a third party subcontractor to manufacture
the resulting materials.
UDC has developed phosphorescent OLED (PHOLED) technology and DuPont has
worked on solution-based processing (such as ink jet printing). Under a
cross-license agreement, DuPont will make an initial payment and pay UDC a
running royalty for products sold that use UDCs background phosphorescent
emitter, transparent cathode and ink jet printing technologies.
SANYO Electric will begin production of HIT (heterojunction with intrinsic
thin-layer) photovoltaic modules at a facility in Monterrey, Mexico,
beginning summer 2003. SANYO Energy (Mexico) will be responsible for
production and SANYO Energy (USA) for sales.
The SANYO HIT photovoltaic module claims the worlds top cell energy
conversion rate of 18.5%. The module has been chosen to provide 482kW worth
of solar power for a system total of 675kW to be installed on the Moscone
Center, located in San Francisco, California. This solar power generation
system is the first stage of a reusable energy project to be implemented by
the city of San Francisco. The Moscone is the site of many exhibitions
including the annual SEMICON West show organised by SEMI.
Infineon Technologies presented nine reports on technology development and
new research to the 2002 International Electron Devices Meeting (IEDM),
December 9-11, 2002. The presentations include three papers on extending the
design and fabrication of DRAM chips to feature sizes of less than 70nm.
Several additional papers covered silicon germanium circuit fabrication (a
5psec bipolar transistor), micro-electo-mechanical systems (MEMS) for radio
frequency applications (with Nokia), printing circuits on plastic films and
completely electronic detection of DNA samples using integrated "biochip"
CMOS circuits.
One of the memory technology papers described a fully depleted surrounding
gate transistor (SGT) for 70nm DRAM and beyond. The vertical array device
potentially enables memory chips with more than 200% greater capacity than
today without changing the size of the chip.
Another of the memory developments is a fully integrated Al2O3 trench
capacitor DRAM for a sub-100nm process. This aims at replacing the standard
nitride-oxide with Al2O3 as the "high-k" capacitor dielectric in the trench.
The final DRAM paper is on feature scale models of trench capacitor etch
rate and profile to enable efficient design of high-density trench
technology DRAM memory arrays.
The paper on polymer gate dielectric pentacene TFTs and circuits on flexible
substrates details what Infineon researchers and industry partners think may
be the fastest circuits ever fabricated on flexible organic (and thus
low-cost) polymer materials.
SUSS MicroTec says it offers a cost-effective alternative to high-resolution
electron beam lithography for printing sub-100nm geometries with three
embossing tools based on its mask aligner and bonding tools.
"Nanoimprinting" uses nanoscale patterns to stamp or print designs on chip
surfaces. The technique is being developed to create subwavelength optical
elements for use in optical communication devices. The company also suggests
applications in BioMEMS and nanotechnology.
Currently SUSS has three imprint lithography methods for transferring the
image of the nanostructures into a polymer layer - embossing, stamping and
moulding. These techniques can be used either at wafer level when a only
single level is required or at chip or larger area level when several layers
with accurate overlay is required.
One of SUSS MicroTecs methods uses stepper technology and the other two
apply different embossing techniques. The techniques are based on SUSS FC
150 device bonder, MA6 mask aligner and SB6 substrate bonder.
Hot embossing at the chip or larger area level is called step and print.
Cold embossing (also called soft lithography) is referred to as step and
flash. These techniques can be implemented using a properly configured
device bonder (flip-chip bonder) in a step and print or step and flash
method. At wafer level, cold embossing is achieved with an adapted contact
printing mask aligner while hot embossing is achieved using a substrate
bonder, which is commonly used for micro-electro-mechanical system (MEMS)
manufacturing.
The FC 150 device bonder is used for a submicron alignment process similar
to an optical stepper at the chip or larger area level. The tool uses UV
curing (a photochemical process by which monomers harden or cure upon
exposure to ultraviolet radiation) with a localised exposure area of
15-20mm2 square, at a wavelength of 365nm and an intensity of more than
100mW/cm2. The UV curing can also be replaced by a heating tool to perform
hot embossing in a step and print mode.
The MA6 mask aligner was designed for single or double sided embossing of
micro-optical elements. This provides aligned single- or multi-layer wafer
level cold embossing. The embossing uses a newly developed hybrid inorganic
polymer called Omorcer. The MA6 is capable of printing resists from less
than 0.1microns to a few 100microns thick at a resolution of less than
0.1micron. Top or bottom side alignment and specific UV curing wavelength
can also be selected.
The SB6 substrate bonder can provide hot embossing at a low cost. It works
in controlled atmospheres with a high bond force of up to 9kN and a
temperature range up to 550C. If alignment is needed, a transport fixture
can provide an interface between the aligner and the substrate bonder.
