TI Produces 90nm Baseband Device
The process includes the ability to make circuits with up to nine layers of copper. The company designed the technology to enable integration of a wide array of analogue and radio frequency (RF) components for wireless communications applications.
The low-k dielectric is an organo-silicate glass (OSG) with a k-value of 2.8. The technology is TIs third to use gates with a plasma nitrided oxide (PNO) for the core transistors, which will be scaled to 1.2nm thick for the first time. PNO is used to maintain reliability and minimise gate leakage.
The process includes embedded SRAM with densities up to 800kbits/mm2. In 2005, TI plans to add 90nm embedded ferroelectric memory (FRAM) technology; a low cost, high density, low-power, non- volatile memory alternative.
Rather than use a single pair of CMOS transistors optimised to support all circuit functions, TIs 90nm process makes it possible to use a collection of "tuned" transistors for different functions. The optimisation is achieved through adjustments to the transistors gate length, threshold voltage, gate oxide thickness or bias conditions. TI expects this capability to reduce system power by two to three times in future products while simultaneously increasing performance.
TI will offer several 90nm process flows to meet the needs for lower power operation, longer battery life and less heat generation; a balance of performance and power consumption; or pure high-performance computing.
The high performance flow will be used to support Sun Microsystems next generation UltraSPARC processor used in high-end workstations and servers. TI estimates that UltraSPARC performance will double over todays solutions.
