Process Development
the minimum for fabrication costs by a factor of up to ten. The new
[email protected] programme will enable universities and research laboratories
worldwide to fabricate very small designs at a cost of a few hundred euro.
IMEC will offer access to ASIC design technologies and AMI Semiconductor
BVBA Belgium (AMIS) will deliver volume production runs in different
technologies (advanced CMOS, high voltage CMOS and SiGe BiCMOS).
ASIC prototyping is offered through pre-scheduled multi-project wafer
(MPW) runs whereby several designs are merged on the same mask set, so
that expensive mask and wafer costs are shared between customers. The new
deal reduces the minimum chargeable area from 5-10mm2 to 1mm2, opening MPW
cost savings up to smaller designs from under- and post-graduate students.
Toshiba and Infineon Technologies have jointly developed a 32Mbit
ferroelectric RAM (FeRAM). The companies claim this as the highest
capacity so far achieved. This is the first result of a joint development
programme initiated by the companies in 2001.
The non-volatile memory device uses a "chained" cell architecture that can
be extended to higher densities. The chain-cell structure links together
eight cells to form a cell block. Each cell configures a ferroelectric
capacitor and a field effective transistor (FET) in parallel, not in the
usual series structure used in FeRAM.
FeRAM offers low power consumption and an immense number of read and write
cycles but has been of limited application in terms of density and
fabrication difficulty. The 32Mbit FeRAM was built on a 0.2micron process.
The FeRAM has an overall area of only 96mm2 - half that of a conventional
device with the same sized cell. The controller area of the chip is cut to
34% of the total chip, the smallest proportion yet achieved.
Details were presented at the International Solid State Circuits
Conference (ISSCC) this week.
Singapore IC test and assembly service company ST Assembly Test Services
has completed qualification of its front-end assembly operations for
packaging chips from 300mm wafers.
The company implemented an automated front-of-line (FOL) in-line module to
eliminate the handling risks associated with heavy 300mm wafers. This is
achieved by an automated taping of the wafer before the wafer-thinning
backgrind process. Upon completion, the wafers are automatically mounted
onto metal rings. The wafer is then supported for the detaping process in
preparation for the wafer saw operation.
The in-line module is capable of thinning 300mm wafers down to 100microns
for stacked die and SiP applications. STATS established its 300mm assembly
capabilities in 2002 and recently completed internal qualification.
Several of STATS customers are in the process of qualifying its 300mm
assembly line.
Microsystem producer Corning IntelliSense and Northrop Grummans
Electronic Systems sector are collaborating on a US Air Force Research
Laboratory/Defense Advanced Research Projects Agency (AFRL/DARPA)
sponsored programme on RF MEMS (micro-electro-mechanical system)
improvement.
The aim is to design, model and fabricate low cost, highly reliable RF
MEMS devices for US Department of Defense (DoD) applications. RF MEMS use
the mechanical and electrical attributes of MEMS technology to address
shortcomings of traditional semiconductor devices. For many wireless
applications, RF MEMS offer smaller, lower power, and higher performing
communication products.
Texas Instruments entire logic portfolio is now available in Pb-free
packaging according to the J-STD-020B (250C max reflow) standard. The
leadframe-based packages use a nickel palladium gold (NiPdAu) finish
compatible with both SnPb and SnAgCu solders. SnAgCu is used in BGAs.
