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High-k Goes To Metal Gate, High-Q Inductors From Post-processing

IMEC has described two developments in semiconductor R&D with the extension of its industrial affiliation programme (IIAP) on high-k dielectrics for (sub)-65nm devices to provide solutions for the implementation of metal gate stacks in planar-scaled CMOS and development of a post-processing technique to create high-Q inductors.
High-k goes to metal gate, high-Q inductors from post-processing
IMEC has described two developments in semiconductor R&D with the extension of its industrial affiliation programme (IIAP) on high-k dielectrics for (sub)-65nm devices to provide solutions for the implementation of metal gate stacks in planar-scaled CMOS and development of a post-processing technique to create high-Q inductors.


Current standard gate stacks use polysilicon above the dielectric layer. The implementation of high-k stacks with polysilicon electrodes is currently being pursued at IMEC, starting from a baseline process with 65nm gate length transistors and dielectric layers with an EOT (equivalent oxide thickness) in the range of 1.6nm to 1.4nm, targeting applications where low gate leakage is required. However, scaling of polysilicon gate stacks with an EOT of 1nm and below gives rise to serious concerns for the yield and reliability of these layers. This necessitates the introduction of metal gate electrodes for advanced applications.


The activities on the implementation of metal gates will start from development of a 45nm process platform. Both single and dual metal gate options will be pursued and implemented in CMOS devices with a gate length of 20nm (and below if feasible). Hf-based high-k dielectric layers with EOT levels around 1nm will be used at the start of the programme. Gradually, the EOT and gate dimensions will be decreased and the related limitations will be investigated.


The final realisation of the programme aims at sub-20nm transistors with dielectric stacks having EOT values close to 0.5nm. Possible integration of alternative high-k dielectrics with k values that exceed the range that can currently be obtained with Hf-based materials may have to be considered.


"The metal gate programme builds on our expertise developed in both the high-k and HikDIP (integration of high-k gate stacks in advanced devices) IIAPs, which aim to solve the problems arising when integrating high-k gate dielectric and polysilicon gate stack CMOS," reports Gilbert Declerck, president and CEO of IMEC.


The programme is scheduled to start in mid 2003 and is expected to run until the end of 2006. Target partners are leading semiconductor manufacturers, whether they already participate in an IIAP or not.


IMEC has also introduced wafer-level packaging techniques on top of back-end-of-line (BEOL) IC processes to realise cost-effective high-Q inductors. Q represents the energy retention of the inductive element. Energy is lost through electrical resistance. Target applications for the high-Q inductors include RF and microwave systems.


The low Q (quality) factors (typically 5 to 10) of traditional on-chip inductors are an important roadblock in the further development of silicon-based technologies at RF and microwave frequencies. IMEC has developed a inductor fabrication technique on top of processed ICs by post-processing wafer-level thin-film layers of Cu metallisation and low-k dielectrics on top of the passivation of a five metal layer back-end-of-line Cu/oxide wafers.


Q-factors of more than 30 can be obtained. Target frequencies of the thin-film inductors cover the 1-20GHz frequency range. A 1nH spiral inductor with a Q factor topping 30 in a frequency range from 2.6-8.6GHz has been demonstrated with a peak Q of 38 around 4.7GHz and a resonance frequency of 29GHz. The combination of post-processed passives with patterned ground shields underneath the spiral inductors, further increases the Q factor and significantly extends the performance to higher frequencies.


The post-processing is compatible with both Al and Cu BEOLs and induces no performance shift in the underlying interconnect layers and devices. Since thin-film wafer-level packaging techniques are used, the solution is cost effective and consumes no additional silicon real estate. Furthermore, models for the inductors are available enabling co-design of post-processed inductors and RF circuits.


Another application of the thin-film technique is to mount and interconnect miniature system-in-package solutions for wireless telecoms.

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