Process Development
dielectrics for (sub)-65nm devices to provide solutions for the
implementation of metal gate stacks in planar-scaled CMOS. The current
standard gate stack uses polysilicon above the dielectric.
The implementation of high-k stacks with polysilicon electrodes is currently
being pursued at IMEC, starting from a baseline process with 65nm gate
length transistors and dielectric layers with an EOT (equivalent oxide
thickness) in the range of 1.6nm to 1.4nm, targeting applications where low
gate leakage is required. However, scaling of polysilicon gate stacks with
an EOT of 1nm and below gives rise to serious concerns for the yield and
reliability of these layers. This necessitates the introduction of metal
gate electrodes for advanced applications.
The activities on the implementation of metal gates will start from
development of a 45nm process platform. Both single and dual metal gate
options will be pursued and implemented in CMOS devices with a gate length
of 20nm (and below if feasible). Hf-based high-k dielectric layers with EOT
levels around 1nm will be used at the start of the programme. Gradually, the
EOT and gate dimensions will be decreased and the related limitations will
be investigated.
The final realisation of the programme aims at sub-20nm transistors with
dielectric stacks having EOT values close to 0.5nm. Possible integration of
alternative high-k dielectrics with k values that exceed the range that can
currently be obtained with Hf-based materials may have to be considered.
"The metal gate programme builds on our expertise developed in both the
high-k and HikDIP (integration of high-k gate stacks in advanced devices)
IIAPs, which aim to solve the problems arising when integrating high-k gate
dielectric and polysilicon gate stack CMOS," reports Gilbert Declerck,
president and CEO of IMEC.
The programme is scheduled to start in mid 2003 and is expected to run until
the end of 2006. Target partners are leading semiconductor manufacturers,
whether they already participate in an IIAP or not.
IMEC has also introduced wafer-level packaging techniques on top of
back-end-of-line (BEOL) IC processes to realise cost-effective high-Q
inductors. Q represents the energy retention of the inductive element.
Energy is lost through electrical resistance. Target applications for the
high-Q inductors include RF and microwave systems.
The low Q (quality) factors (typically 5 to 10) of traditional on-chip
inductors are an important roadblock in the further development of
silicon-based technologies at RF and microwave frequencies. IMEC has
developed a inductor fabrication technique on top of processed ICs by
post-processing wafer-level thin-film layers of Cu metallisation and low-k
dielectrics on top of the passivation of a five metal layer back-end-of-line
Cu/oxide wafers.
Q-factors of more than 30 can be obtained. Target frequencies of the
thin-film inductors cover the 1-20GHz frequency range. A 1nH spiral inductor
with a Q factor topping 30 in a frequency range from 2.6-8.6GHz has been
demonstrated with a peak Q of 38 around 4.7GHz and a resonance frequency of
29GHz. The combination of post-processed passives with patterned ground
shields underneath the spiral inductors, further increases the Q factor and
significantly extends the performance to higher frequencies.
The post-processing is compatible with both Al and Cu BEOLs and induces no
performance shift in the underlying interconnect layers and devices. Since
thin-film wafer-level packaging techniques are used, the solution is cost
effective and consumes no additional silicon real estate. Furthermore,
models for the inductors are available enabling co-design of post-processed
inductors and RF circuits. Another application of the thin-film technique is
to mount and interconnect miniature system-in-package solutions for wireless
telecoms.
AMD researchers claim to be the first in the semiconductor industry to
achieve critical research milestones for next-generation transistor
development.
Among the achievements in the laboratory is a high-performance transistor
that is up to 30% faster than the best-published PMOS (P-channel metal-oxide
semiconductor) transistor. The transistor employs proprietary technologies
involving fully depleted silicon-on-insulator structures.
Related research has demonstrated a strained silicon transistor achieving
20-25% higher performance than conventional strained silicon devices through
the use of metal gates, also claimed as a first.
These achievements are expected by AMD to play a critical role in
semiconductor manufacturing in the second half of this decade. Both will be
presented at this years VLSI Symposium, June 11-12, 2003, in Kyoto, Japan.
Motorola says it has demonstrated the worlds first 4Mbit memory based on
silicon nanocrystals. The company sees the fully functional test chip as a
major milestone in the search for successors to floating gate-based flash
memories. Many believe Flash will not continue to scale to smaller
geometries.
Silicon nanocrystal memories are part of a class of techniques called thin
film storage. Motorola has developed techniques designed to help simplify
the manufacture of these memories. Using traditional deposition equipment,
researchers at Motorolas DigitalDNA Laboratories deposited silicon
nanocrystals resembling 50Angstrom diameter spheres between two layers of
oxide. The silicon spheres are engineered to hold and prevent lateral
movement of charge to other isolated nanocrystals. This is expected to
increase reliability and scalability because a single oxide defect does not
lead to complete charge loss as in a conventional floating gate non-volatile
memory.
Motorola built the test array on 200mm wafers using its 90nm process. The
key challenge researchers overcame was getting the nanocrystals to grow
repeatedly to consistent size and density. If the nanocrystals are too small
or too dispersed, then the memory device will not hold sufficient charge
density. The proper charge density is what allows the memory to detect
"on/off" states. If the nanocrystals are too large or too dense, the
electrons may move either to other nanocrystals or leak through defects in
the tunnel oxide beneath the nanocrystals. By experimenting with different
process chemicals and modifying conditions such as temperature, pressure and
time, Motorola developed a method to repeatedly grow the nanocrystals with
existing equipment. Researchers may now focus on reduced die sizes and
tightened specifications to be ready for potential products in 2004.
At 90nm and smaller, manufacturing floating gate-based Flash becomes
impractical. At those dimensions, the chip area spent on the 9-12V high
voltage transistors needed to write and erase the flash becomes too
expensive. Further, engineers cannot reduce the high voltage in
floating-gate based Flash without compromising reliability, at the risk of
memory failures and loss of data. Motorola is also investigating
magnetoresistive random access memory (MRAM) as an alternative to Flash.
A research team at Sheffield Hallam University in the UK has been exploring
a range of options for cutting the costs of producing photovoltaic (PV)
cells. These include the use of a low-cost electrodeposition method, less
reliance on expensive semiconductor materials, and the identification of
alternative solar cell devices and manufacturing techniques offering higher
conversion efficiencies.
In the past, limited understanding of the scientific principles underlying
PV meant that average solar cell efficiencies only improved from 15.9% to
16.5% between 1992 and 2001 for cadmium telluride based solar cells. By
formulating a new "model" to describe the photovoltaic activity of CdTe and
copper indium gallium di-selenide (CIGS) materials in solar cells, the
Sheffield Hallam Team has significantly improved this understanding and
produced devices with 18% efficiency. This has opened up the prospect of new
solar cells being developed commercially with higher conversion efficiencies
than those currently available.
Team leader Dr IM Dharmadasa reports: "Weve already applied for two patents
and are preparing the final draft of the third patent in connection with our
work, but theres a lot more science to be explored that could increase
conversion efficiencies to over 20% in the near future".
The research team included physicists, chemists, material scientists and
engineers. Funding of GBP 104,632 has come from the UK Engineering and
Physical Sciences Research Council and a further GBP140,000 from the
university.
The model is based on the authors experimental work on glass/conducting
glass/CdS/CdTe/metal solar cells and other work in the literature
(Semiconductor Science Technology, December 2002). The model explains the
device behaviour in terms of a combination of a hetero-junction and a large
Schottky barrier at the CdTe/metal interface. The researchers believe that
the proposed model explains almost all the experimental results more
satisfactorily than the currently assumed p-n junction model.
Following new guidelines based on the model, the researchers have fabricated
improved devices producing open circuit voltage (Voc) values of more than
600mV, fill factor (FF) values over 0.60 and a short-circuit current density
(Jsc) of more than 60mA/cm2 for the best devices.
QinetiQ has developed an optical hybrid technology that uses a hollow
waveguide (HWG) to improve performance while reducing expenditure. The HWG
has the potential to cut more than 50% off the cost of complete optical
circuits, says Qinetiq.
The HWG is etched or cut from a flat substrate to provide a guide channel in
the material. Coating the guide walls to alter their optical properties can
enhance the performance. A lid is attached to provide the fourth guide wall.
HWGs complement traditional "rib" or "ridge" structure to maintain all the
usual performance criteria. It also allows greatly simplified assembly of
components or modules. For example, the insertion of a component into a
guide now involves only two interfaces - one is the guide to component
interface and the second the component to guide interface (in both cases the
guide is air). This compares with the four interfaces involved in the
conventional rib waveguide (guide to air to component to air to guide).
The unique technology enables light to be guided directly from device to
device across a large area. This overcomes the problems of beam divergence
and alignment accuracy.
Another major benefit of the HWG is that monolithic functions can be
integrated during the same fabrication process that is used to create the
hollow waveguides. These might include MEMS devices, multi-mode interference
(MMI) devices and free space component functions.
QinetiQ offers a design service for HWG integration into specific
applications. QinetiQ can also provide access to substrate fabrication and
designs may be transferred directly into customer facilities, or passed to
preferred partners for high volume manufacture.
Diodes Incorporated has developed an ultra-low leakage, high voltage
Schottky barrier rectifier process. The new process is expected to allow
development of Schottky barrier rectifiers having reverse breakdown voltage
ratings of up to 200V.
Leakage currents are said to be low enough to suit many high efficiency
switch-mode power supply (SMPS) applications such as adaptors, desktops and
servers. The low forward voltage drop of the Schottky barrier rectifier
makes it more efficient than traditional P-N junction devices such as
ultra-fast recovery rectifiers. In addition, the lower forward drop of the
Schottky device results in lower heat dissipation, which allows for greater
miniaturisation of portable products.
The new products are also expected to have broad appeal in automotive
applications where the low breakdown voltage of traditional Schottkys is not
suitable due to temporary high voltage transients coming from inductive
elements such as fans, solenoids and alternators.
Cambridge Display Technology (CDT) says that it has dramatically improved
the life performance of display devices based on light emitting polymer
(LEP) technology, achieving more than 11,000 hours of operation for its blue
polymer research devices. This represents a trebling of lifetime over the
past 12 months for the blue research devices. The longer operating life is
due to advances in LEP material formulation, improved deposition processes
for the polymer and other materials and innovative device structures. The
improvements in processes and structures are directly transferable to red,
green, white and other polymer material colours. CDT expects that many of
these improvements will be transferable to full manufacturing processes.
CEO Dr David Fyfe reports: "We focused on the blue material since it is
vital to providing the full colour capability essential for mainstream
display markets such as television and personal computing along with the
exploding market for multimedia-enabled cell phones, PDAs and other mobile
products. Even though longer lifetimes are still needed, these results are a
significant milestone towards the commercialisation of the LEP technology."
The lifetime is measured as the time from initial brightness to half the
initial brightness. The method used is based on the industry standard for
measuring the decrease in brightness of emissive-type displays, such as
plasma, CRTs, and LEPs, which are a type of organic light-emitting display
(OLED). Testing at higher brightness and operating temperature was used due
to the long operating time needed to measure the result and correlated with
ongoing testing at room temperature and typical commercial display
brightness levels of 100cd/m2.
SAES Getters and its Molecular Analytics subsidiary have released onto
market their AirSentry-IMS AMC System. The tool is designed to provide
complete real time monitoring of cleanroom air quality. Included in the
monitoring of amines and acids and full determination and speciation of
volatile organic contaminants. The system includes Molecular Analytics ion
mobility spectrometer for the determination of ammonia, total amines and
total acids. The determination and speciation of the volatile organic
contaminants is carried out by a process gas chromatograph equipped with
thermo desorption capability and by a flame ionisation detector developed by
SAES Getters. The system samples up to 16 points in the cleanroom area.
Engineers and technicians at International SEMATECH (ISMT) have pioneered an
etch process that allows the removal of high-k film from a wafer surface
without damaging the underlying silicon. This process was able to remove
hafnium dioxide (HfO2) after post-deposition annealing without causing
damage to, or loss of, silicon material in the source-drain region. This
silicon material is critical to the transistor series resistance and thus
the maximum current it can sustain. The process was conducted within ISMTs
Advanced Technology Development Facility on 200mm wafers at the 130nm node.
A high-k material has a dielectric constant (k value) larger than that of
silicon dioxide, the industry standard gate dielectric material, thereby
allowing retention of the gate capacitance even as the physical dielectric
thickness increases. This physical thickness difference results in high-k
materials having much lower leakage current than silicon dioxide at an
equivalent electrical thickness.
High-k materials are required for continued gate dielectric scaling in high
performance applications and for reduced leakage current in lower power
applications such as mobile consumer products.
The high-k milestone was achieved in January 2003 by the Advanced Gate Clean
project team (Naim Moumen (IBM) and Joel Barnett (ISMT)) using an innovative
etch process to remove hafnium dioxide (HfO2) deposited by metallorganic
chemical vapour deposition (MOCVD) and atomic layer deposition (ALD)
processes.
Samsung Electronics announced mass production of a four-chip multi-chip
package (MCP) for mobile handsets. The company also announced a new
integrated software system that greatly reduces the development time of MCP,
system in package (SiP) and system on chip (SoC) designs by enabling
simultaneous design of semiconductor circuits and packages.
The MCP is 1.4mm in height, which is 0.2mm greater than a conventional
single-chip component of 1.2mm. The MCP can include various memory products
for mobile solutions: SDRAM, SRAM, UtRAM (Samsungs pseudo-SRAM product),
and NAND/NOR Flash memory. The new four-chip MCP is available in two
combinations - a NOR Flash based combination (two 64Mbit NOR Flash, a
128Mbit NAND Flash and a 64Mb UtRAM) and a NAND Flash based MCP (128Mbit
NAND Flash memory, 64Mbit UtRAM, 32Mbit UtRAM and 8Mbit SRAM).
Tokyo Electron (TEL) and Teseda have developed an integrated IC Design For
Testability (DFT) system. A demonstration system has been constructed
consisting of TELs P-8XL wafer prober and Tesedas Validator 500
DFT-focused validation system. Test costs are estimated at less than $200
per pin. The combined system enables wafer tests on chips equipped with DFT
circuits. The system is designed to make it possible to reduce both test
costs and test design man-hours.
Tesedas president and CEO Steve Morris says: "The DFT cell-demo
validation system eliminates the need for wafer package cycle latency time.
I look forward to working with TEL to develop other DFT test applications in
the future as well."
