News Article
Process Development
TSMC announced new production data on its 0.13micron processes as well as a status report for 90nm. More than 230 product designs have been taped out to TSMCs 0.13micron processes and more than 100,000 0.1micron wafers shipped to date.
TSMC announced new production data on its 0.13micron processes as well as a status report for 90nm. More than 230 product designs have been taped out to TSMCs 0.13micron processes and more than 100,000 0.1micron wafers shipped to date. TSMC claims its 0.13micron low-k process technology is the first in the foundry industry to pass customer product qualifications
and enter volume production. In particular, LSI Logic and Agere Systems have formally announced product qualification on the low-k, 0.13micron process.
The foundry has also recorded more than 20 customer design projects on its 90nm process that are at various stages. Production for customers using
TSMCs Nexsys 90nm technology with copper and low-k dielectrics on 300mm wafers is expected to start in Q3 2003. Fully functional 90nm test chips were successfully produced in Q4 2001.
TSMC anticipates shipping more than 400,000 200mm equivalent wafers on its 0.13micron processes this year. By the end of 2003, the monthly installed
capacity for 0.1-micron technology at TSMC Fab 12, a 300mm-wafer fab, is expected to reach approximately half of the companys total monthly installed capacity for 0.13micron technology. The company expects 20% of
its revenues will come from 0.13micron products in 2003.
Advanced Semiconductor Engineering (ASE) has successfully qualified its wire bond BGA and flip chip BGA for use with TSMCs all-copper, 0.13-micron low-k (k=2.9) dielectric process. Package body sizes up to
37.5x37.5mm are covered.
"The accomplishment marks a significant milestone for ASE, as the industryin general has reported difficulties qualifying packages on low-k," says
Dr Ho-Ming Tong, vice president of Advanced
Technologies. "ASE has gained a breakthrough after extensive research and development efforts with TSMC,
using new and advanced techniques. The use of flip chip packaging further enhances the performance of the copper low-k chip as the I/O pads are distributed all over the surface of the chip, allowing optimisation of the circuit path and reduction of signal inductance."
NEC Electronics has selected Applied Materials Black Diamond and BLOK low-k dielectric films for manufacturing NECs UX6 chips. The Black Diamond and BLOk films are fully qualified for volume production, which is expected to begin in July 2003.
NECs UX6 chips are designed using 90nm process technology and feature 100mn transistors, nine levels of copper interconnects and clock speeds
above 1GHz.
NEC developed its UX6 90nm process technology for next-generation high-performance, low-power ASIC designs for applications such as broadband communications, high-end computing and storage systems and
mobile computing devices.
Both Black Diamond and BLOk films are deposited using Applied Materials high-throughput Producer CVD system.
Toshiba has introduced multi-chip packages (MCPs) with five or six chips stacked inside ball grid arrays (BGA). The packages measure 9x12x1.6mm.
The MCPs can contain various combinations of NOR Flash, NAND Flash, static RAM (SRAM), and pseudo SRAM (PSRAM) to meet the complex memory requirements of digital camera phones and feature-rich 3G cellphones.
Cellphone designers typically prefer NOR Flash memory for code storage and low-power SRAM or fast, cost-effective PSRAM for working memory. Recently,
NAND Flash has been adopted for additional application and data storage because of its low cost-per-bit.
ASIC supplier LSI Logic has developed a proprietary "Statistical Post-Processing" test methodology for advanced defect screening in deep
sub-micron designs. The technique was developed in collaboration with Portland State University. The approach has been implemented in LSI
Logics ASIC production environment for its 0.18micron (G12) and 0.11micron (Gflx) process flows. The company reports a 30-60% decrease in failure rate measured by defects per million (DPM) units and early failure
rate (EFR) values. The company believes that this defect screening approach is especially suited to applications often found in the communications and storage markets.
Statistical Post-Processing identifies unusual data values or statistical "outliers" by using raw data from automatic test equipment (ATE) and wafer
sort maps, making it possible to isolate defective parts off-tester.
Post-processing modules have been developed for all major defect categories that are designed to estimate and factor out the defect-free contributions so the defects can be clearly identified and screened. This
level of defect screening efficiency cannot be achieved with traditional on-tester methods or burn-in. "User-definable" adaptive test thresholds
have been implemented to maximise the confidence in maturity of the technologies.
Tessera is claiming the worlds first chip-scale packaging technology for integrated radio frequency (RF) module production with its Pyxis platform.
The technology builds upon Tesseras microBGA package while integrating various other features such as flip-chip, integrated passives in silicon and on polyimide, as well as novel electromagnetic interference (EMI)
shielding. Along with a new licence, Tessera is offering a full suite of RF services, design tools and libraries.
The platform is designed to support and integrate a multitude of functions such as power amplifiers, transceivers, filters and switches. The first
implementation of the technology family - the Pyxis Power Amplifier (PA) platform - integrates tri-band GSM/GPRS power amplifiers with surrounding
passive components. By suppressing the need for expensive gallium arsenide (GaAs) thermal vias and integrating inductors on low-cost polyimide tape
and capacitors on a low-grade silicon chip, the Pyxis PA delivers significant size and cost advantages. When compared with competitive alternatives, such as ceramic and laminate modules, the platform is
claimed to provide 50% cost, 60% height, and 75% area reductions.
Pyxis is aimed at handset makers for new revenue-generating features- such as MP3, GPS, Wi-Fi and digital imaging. Licences are available today.
Production ramp-up technology, design kits/libraries and associated assembly line support services will be widely available for transfer in mid-2003.
and enter volume production. In particular, LSI Logic and Agere Systems have formally announced product qualification on the low-k, 0.13micron process.
The foundry has also recorded more than 20 customer design projects on its 90nm process that are at various stages. Production for customers using
TSMCs Nexsys 90nm technology with copper and low-k dielectrics on 300mm wafers is expected to start in Q3 2003. Fully functional 90nm test chips were successfully produced in Q4 2001.
TSMC anticipates shipping more than 400,000 200mm equivalent wafers on its 0.13micron processes this year. By the end of 2003, the monthly installed
capacity for 0.1-micron technology at TSMC Fab 12, a 300mm-wafer fab, is expected to reach approximately half of the companys total monthly installed capacity for 0.13micron technology. The company expects 20% of
its revenues will come from 0.13micron products in 2003.
Advanced Semiconductor Engineering (ASE) has successfully qualified its wire bond BGA and flip chip BGA for use with TSMCs all-copper, 0.13-micron low-k (k=2.9) dielectric process. Package body sizes up to
37.5x37.5mm are covered.
"The accomplishment marks a significant milestone for ASE, as the industryin general has reported difficulties qualifying packages on low-k," says
Dr Ho-Ming Tong, vice president of Advanced
Technologies. "ASE has gained a breakthrough after extensive research and development efforts with TSMC,
using new and advanced techniques. The use of flip chip packaging further enhances the performance of the copper low-k chip as the I/O pads are distributed all over the surface of the chip, allowing optimisation of the circuit path and reduction of signal inductance."
NEC Electronics has selected Applied Materials Black Diamond and BLOK low-k dielectric films for manufacturing NECs UX6 chips. The Black Diamond and BLOk films are fully qualified for volume production, which is expected to begin in July 2003.
NECs UX6 chips are designed using 90nm process technology and feature 100mn transistors, nine levels of copper interconnects and clock speeds
above 1GHz.
NEC developed its UX6 90nm process technology for next-generation high-performance, low-power ASIC designs for applications such as broadband communications, high-end computing and storage systems and
mobile computing devices.
Both Black Diamond and BLOk films are deposited using Applied Materials high-throughput Producer CVD system.
Toshiba has introduced multi-chip packages (MCPs) with five or six chips stacked inside ball grid arrays (BGA). The packages measure 9x12x1.6mm.
The MCPs can contain various combinations of NOR Flash, NAND Flash, static RAM (SRAM), and pseudo SRAM (PSRAM) to meet the complex memory requirements of digital camera phones and feature-rich 3G cellphones.
Cellphone designers typically prefer NOR Flash memory for code storage and low-power SRAM or fast, cost-effective PSRAM for working memory. Recently,
NAND Flash has been adopted for additional application and data storage because of its low cost-per-bit.
ASIC supplier LSI Logic has developed a proprietary "Statistical Post-Processing" test methodology for advanced defect screening in deep
sub-micron designs. The technique was developed in collaboration with Portland State University. The approach has been implemented in LSI
Logics ASIC production environment for its 0.18micron (G12) and 0.11micron (Gflx) process flows. The company reports a 30-60% decrease in failure rate measured by defects per million (DPM) units and early failure
rate (EFR) values. The company believes that this defect screening approach is especially suited to applications often found in the communications and storage markets.
Statistical Post-Processing identifies unusual data values or statistical "outliers" by using raw data from automatic test equipment (ATE) and wafer
sort maps, making it possible to isolate defective parts off-tester.
Post-processing modules have been developed for all major defect categories that are designed to estimate and factor out the defect-free contributions so the defects can be clearly identified and screened. This
level of defect screening efficiency cannot be achieved with traditional on-tester methods or burn-in. "User-definable" adaptive test thresholds
have been implemented to maximise the confidence in maturity of the technologies.
Tessera is claiming the worlds first chip-scale packaging technology for integrated radio frequency (RF) module production with its Pyxis platform.
The technology builds upon Tesseras microBGA package while integrating various other features such as flip-chip, integrated passives in silicon and on polyimide, as well as novel electromagnetic interference (EMI)
shielding. Along with a new licence, Tessera is offering a full suite of RF services, design tools and libraries.
The platform is designed to support and integrate a multitude of functions such as power amplifiers, transceivers, filters and switches. The first
implementation of the technology family - the Pyxis Power Amplifier (PA) platform - integrates tri-band GSM/GPRS power amplifiers with surrounding
passive components. By suppressing the need for expensive gallium arsenide (GaAs) thermal vias and integrating inductors on low-cost polyimide tape
and capacitors on a low-grade silicon chip, the Pyxis PA delivers significant size and cost advantages. When compared with competitive alternatives, such as ceramic and laminate modules, the platform is
claimed to provide 50% cost, 60% height, and 75% area reductions.
Pyxis is aimed at handset makers for new revenue-generating features- such as MP3, GPS, Wi-Fi and digital imaging. Licences are available today.
Production ramp-up technology, design kits/libraries and associated assembly line support services will be widely available for transfer in mid-2003.
