Philips Electronics has developed a new Flash memory option for its 0.18micron baseline CMOS process, CMOS18. The new CMOS18-FFLV (Fast-Flash, Low-Voltage) option offers memory densities approaching 1Mbit/mm2. Philips claims that CMOS18-FFLV implements the smallest area Flash memory blocks in the industry.

Frans List, strategic program manager for embedded memory at Philips
Semiconductors, reports: "By achieving an optimum combination of memory cell
size and power consumption that reduces peripheral circuit complexity, we
are able to create a complete 16Mbit Flash memory in less than 19mm2 of
silicon."
Power consumption has been reduced through an innovative floating-gate
memory cell that uses Fowler-Nordheim tunneling for both programming and
erasure. This eliminates the high-current charge-pump required for 'channel
hot-electron' programming (the technique used in most other embedded Flash).
Operating voltage ranges from 1.2V to 2.0V. An EEPROM version of the memory
that will offer single-byte erasure and re-programming is currently under
development.
Philips has also designed a special interface for CMOS18-FFLV to simplify
connection to the ARM system bus. The process was developed as part of a
MEDEA+ initiative. CMOS18-FFLV is qualified for production, ready for volume
use later this year. The option will also be supported in Philips' CMOS18
process shrink to 0.15microns.