IXYS subsidiary Clare has a 125mm Si wafer foundry service for high voltage IC (HVIC), micro-electro-mechanical system (MEMS) and silicon on insulator (SOI) products. In particular, Clare is making available 330V BCDMOS SOI-based HVIC process technology, MEMS fabrication with and without integrated HVIC circuitry, and thick film SOI wafers with and without lateral high voltage trench isolation. These capabilities are qualified and currently in production. Clare supports a fully integrated Cadence design environment for the HVIC process. Process and materials specifications, capabilities, design rules and qualification data are also available.

Asymtek and the Micro-Electronic Packaging Lab (MEPL) of the Korea Advanced
Institute of Science and Technology (KAIST) have renewed their two-year
agreement to jointly support dispensing reliability studies for
semiconductor packaging applications. An Asymtek Century C-720 system is
currently in use at MEPL, where several companies are conducting dispensing
tests of underfill materials, solder bump reliability, and the development
of flip chip applications.

An International SEMATECH task force believes that hard pellicles are
suitable for 157nm lithography. The pellicles consist of 800micron thick
layers of modified fused silica which are used to protect photomasks.
"We haven't solved all the problems associated with hard pellicles, but we
now clearly understand the issues and will push forward to solve them," says
Intel assignee Andrew Grenville. Pellicle flatness is a key techical risk
area, according to Grenville.
Soft pellicle development has been hindred by material darkening under 157nm
radiation. Soft pellicles would be the prefered industry solution if
suitable materials could be developed.

SUSS MicroTec has expanded its collaboration with the Max Planck Institute
(MPI) of Microstructure Physics in Halle, Germany. SUSS has delivered its
CL200 fusion bonder to MPI's wafer bonding research facility for testing
silicon on insulator (SOI) and fusion bond applications. The research
facility already uses SUSS spin coater, mask aligner, wafer cleaner and a
substrate thermal compression bonder technology. Present research interests
include electrical properties of bonded interfaces, ultra-high vacuum
bonding for the fabrication of spin-valve transistors and bonding of
compound semiconductors and SOI wafers.

Agere Systems has announced a 90nm ASIC (application specific IC)
semiconductor technology platform targeted at communications applications.
The AGR90 platform includes various types of standard protocols,
serial/deserialiser (SerDes) sub-circuits, encoding schemes, digital signal
processors, I/O (input/output) cells, microprocessors and memory. The
platform is based on TSMC's Nexsys 90nm process.
Agere has begun quoting prices to customers and plans to start designing its
90nm technology into products in Q3 2002. The company will start production
volume manufacturing of 90nm chips next year.

Diodes Incorporated has released a new series of Zener diodes based on a new
high precision process developed by FabTech, a wholly owned subsidiary. The
new process (patents pending) uses ion implant rather than the traditional
high-temperature diffusion. This simplified process offers greater control
over the Zener breakdown voltage (VZ), and greatly reduces other variables
that can occur during the process. Breakdown can be specfied within a broad
range by adjusting the implant dose rather than depending on properties of
the raw silicon wafer substrate. All of the voltages within this range can
be achieved using the same wafer substrate starting material. VZ can be
specified with a tolerance of less than +/-2.5%. Zener diodes developed
using traditional processes can usually only be specified to within +/-5% to
+/-7%. Typical tolerances for most voltages within the new UDZ series have
been measured to be less than 1%. The first product to use the process is
packaged in the sub-miniature SOD-323 form factor. Other products are to be
implemented across a range of package styles, including multi-pin packages
in Zener array configurations.

The US Office of Naval Research (ONR) has awarded Cree two contracts, with a
total value of approximately $14.4m, as part of the Wide Bandgap
Semiconductor Technology Initiative of the US Defense Advanced Research
Projects Agency (DARPA).
The first contract provides for up to $8.8m over an 18 month period for work
directed to microwave and related technologies. This is focused on
development of high quality 100mm semi-insulating substrates supporting the
requirements of both silicon carbide (SiC) MESFET and gallium nitride (GaN)
HEMT microwave devices. Also included is work directed toward development of
new, highly uniform SiC MESFET and GaN HEMT epitaxial processes on larger
diameter wafers and studies correlating material advances with device
performance. The GaN-related work will be performed by a team from the
microwave groups at Cree in Durham NC and Cree Lighting in Goleta CA.
The second contract for up to $5.6m over an 18 month period is for work on
SiC high voltage, high power switching devices for high power conversion and
distribution technology. Cree is directed to develop low defect density
100mm, n-type 4H-SiC substrates that would allow the fabrication of large
area high current, high voltage power devices. Cree will also work to
develop more uniform, thick epitaxial processes required for the fabrication
of devices with blocking voltages in excess of 10kV. Additionally, Cree will
pursue device development focused on high reliability, high voltage SiC PiN
rectifiers and MOSFETs based on these materials.
The contracts include options for the ONR to extend the work by six months
and provide additional funding of up to $2.9m and $1.8m for the two projects
respectively.